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The CCS C Compiler now supports the dsPIC33CH family of devices! The dsPIC33CH family are the first dual core PIC®MCUs available from Microchip, which allows the user to run two independent programs on the same device. Additionally each core has separate clock circuits allowing each core to run different clock frequencies, with the Master core's max frequency being 180MHz (90 MIPS) and the Slave core's max frequency being 200MHz (100 MIPS).
Currently devices are available with the Master core having up to 512 Kbytes of flash program memory and up to 48 Kbytes of data RAM, and the Slave core having up to 72 Kbytes of Program RAM (PRAM) and 16 Kbytes of data RAM. Since the Slave core's program memory is PRAM, its actual program is stored in the Master core's Flash program memory and loaded at run time by the Master core into the Slave core's PRAM. The CCS C Compiler provides the functions load_slave_program() and verify_slave_program() for loading and verifying the Slave core's PRAM. See ex_ch_master.c and ex_ch_slave.c for an example of how to build and load a Slave core's program. Additionally, since the Master core and Slave core have separate data RAM, Microchip provides two methods for the cores to communicate with each other. The first method is a series of Mailbox registers, whose direction and protocol can be programmed with configuration fuses to communicate between the cores. The second method is dedicated to read and write FIFO registers that can be used to communicate between the cores. Both are part of the Master Slave Interface (MSI) peripheral and the CCS C Compiler provides several functions for setting it up, checking the status, as well as reading and writing data to and from the mailbox and FIFO registers.
Some features of the dsPIC33CH family are as follows; the Master core has one 16-bit Timer, six DMA channels, eight SCCP peripherals, two UART peripherals, two SPI peripherals, two I2C peripherals, up to two CAN FD peripherals, two SENT peripherals, one CRC peripheral, one QEI peripheral, four CLC peripherals, four 16-bit High-Seed PWM peripherals, a 12-bit ADC with up to 16 channels, and one 12-bit DAC with Analog comparator peripheral. The Slave core has one 16-bit Timer, two DMA channels, four SCCP peripherals, one UART peripheral, one SPI peripheral, one I2C peripheral, one QEI peripheral, four CLC peripherals, eight 16-bit High-Speed PWM peripherals, a 12-bit ADC with two dedicated ADC cores and one shared ADC core with up to 18 channels, and three 12-bit DAC with Analog comparator peripherals.
The SCCP peripheral is newly combined Input Capture, Output Compare, PWM and 32-bit Timer peripherals. This peripheral can be used as either 2 16-bit Timers or a singular 32-bit Timer, a 16-bit or 32-bit Output Compare, a 16-bit or 32-bit Input Capture, or a 16 PWM. Support has been added to #use pwm() for PCD devices that have SCCP peripherals.
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About CCS:
CCS is a leading worldwide supplier of embedded software development tools that enable companies to develop premium products based on Microchip PIC® MCU and dsPIC® DSC devices. Complete proven tool chains from CCS include a code optimizing C compiler, application specific hardware platforms and software development kits. CCS' products accelerate development of energy saving industrial automation, wireless and wired communication, automotive, medical device and consumer product applications. Established in 1992, CCS is a Microchip Premier 3rd Party Partner. For more information, please visit http://www.ccsinfo.com.
PIC® MCU, MPLAB® IDE, MPLAB® ICD2, MPLAB® ICD3 and dsPIC® are registered trademarks of Microchip Technology Inc. in the U.S. and other countries.
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