CCS C Software and Maintenance Offers
FAQFAQ   FAQForum Help   FAQOfficial CCS Support   SearchSearch  RegisterRegister 

ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

CCS does not monitor this forum on a regular basis.

Please do not post bug Reports on this forum. Send them to support@ccsinfo.com

IOC Port E DsPIC33CH512MP508

 
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion
View previous topic :: View next topic  
Author Message
dyeatman



Joined: 06 Sep 2003
Posts: 1858
Location: Norman, OK

View user's profile Send private message

IOC Port E DsPIC33CH512MP508
PostPosted: Wed Feb 02, 2022 2:31 pm     Reply with quote

PCWHD 5.107
After hours of searching I am unable to find compiler support for IOC for Ports
D&E and I am looking at having to access the CNSTYLE/CNEN1/CNEN0 bits
directly. Anyone see something I am missing other than INT_Default?
_________________
Google and Forum Search are some of your best tools!!!!
jeremiah



Joined: 20 Jul 2010
Posts: 1276

View user's profile Send private message

PostPosted: Wed Feb 02, 2022 3:36 pm     Reply with quote

There's no #INT_CNI or enable_interrupts() options? all of my dspics have those normally.

edit: I usually have:

Code:
#int_cni
void cni_isr(){
   // stuff
}




and in the main stuff like:
Code:
enable_interrupts(INTR_CN_PIN | PIN_B1);
enable_interrupts(INTR_CN_PIN | PIN_B2);
dyeatman



Joined: 06 Sep 2003
Posts: 1858
Location: Norman, OK

View user's profile Send private message

PostPosted: Wed Feb 02, 2022 4:27 pm     Reply with quote

Thank you Jeremiah, I found CNIE but could not make it work so I figured
I was interpreting the name wrong. BTW, how did you set up the (neg/pos)
edge triggering? The edge setting options don't seem to support this.

I can make it work by defining and setting the registers directly but I prefer
using the CCS options if possible. With your confirmation I'll play with it some
more.
_________________
Google and Forum Search are some of your best tools!!!!
jeremiah



Joined: 20 Jul 2010
Posts: 1276

View user's profile Send private message

PostPosted: Wed Feb 02, 2022 6:49 pm     Reply with quote

Most of the chip drivers that support it have other enable_interrupts() options. One of my chips (not the same as yours) has

Code:
#define INTR_CN_PIN              0xC000  // or in a PIN_xx constant
#define INTR_CN_PIN_L_TO_H       0x8000  // or in a PIN_xx constant
#define INTR_CN_PIN_H_TO_L       0x4000  // or in a PIN_xx constant



For example. If your H file doesn't have it but your chip is supposed to support it, you might try pinging CCS support via email for an updated header file. They may have just missed it.
Ttelmah



Joined: 11 Mar 2010
Posts: 18060

View user's profile Send private message

PostPosted: Thu Feb 03, 2022 2:11 am     Reply with quote

Several parts:

On this particular chip, there are separate interrupts for each port.
So CNIA, CNIB, CNIC, CNID & CNIE.
Then on the DsPIC's, interrupt on change needs several registers to
setup. You can specify whether the interrupt is triggered by level, or
by the edge. This is controlled by the CNSTYLE bit, and the contents
of CNEN1x and CNEN0x. Which pin has triggered is in the CNFx register
for each port.
There are five registers for each pin on these chips. I think CCS gave
up on trying to set all of these, so leave it to you to do the configuration
of these. They offer the enable for the pins as Jeremiah shows, but not
control of whether this handles edges or levels. They default to just
handling levels setting the CNEN0X bits, and the master enable. Detection
of the bits in the flag register is left up to you.
Set them up as Jeremiah shows in his first post, using the CNIE
interrupt (for your port E), and then should work. However you have
to manually read/clear the CNFE register.
dyeatman



Joined: 06 Sep 2003
Posts: 1858
Location: Norman, OK

View user's profile Send private message

PostPosted: Thu Feb 03, 2022 7:40 am     Reply with quote

Thanks to both of you! With your help I now have a hybrid of CCS functions
and direct register accesses but it works. Hopefully they will get this cleaned
up more later.
_________________
Google and Forum Search are some of your best tools!!!!
Ttelmah



Joined: 11 Mar 2010
Posts: 18060

View user's profile Send private message

PostPosted: Thu Feb 03, 2022 8:48 am     Reply with quote

Point the lack out to them.
This particular chip family is unusual in supporting the extra edge detect
option, and having separate IOC's on each port. I think the person writing
this originally at CCS put in the parts that the functions used on the other
chips had, but didn't get involved in adding support for this chip's 'extras'.
jeremiah



Joined: 20 Jul 2010
Posts: 1276

View user's profile Send private message

PostPosted: Thu Feb 03, 2022 9:37 am     Reply with quote

dyeatman wrote:
Thanks to both of you! With your help I now have a hybrid of CCS functions
and direct register accesses but it works. Hopefully they will get this cleaned
up more later.


Just keep in mind that they don't monitor these forums aside from general moderation. You definitely want to email them and let them know (or call if you don't like email)
Display posts from previous:   
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion All times are GMT - 6 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Powered by phpBB © 2001, 2005 phpBB Group