synchronization problem with even data but not with odd data

[eliberg]

Hi,
I'm trying to send a packet of 6 bytes from a PIC18F4431 "master" to a PIC18F4431 "slave". The 6 bytes are:
1) sync byte (value:85 -0x55- for all data)
2) data byte (value from 1 to 15)
3) data byte (" ")
4) data byte (" ")
5) MSB CRC8
6) LSB CRC8
The three data bytes are the same byte (just only for redundancy).
I have the synchronization procedure written belowe, with the following problem: when the data byte are odd (1,3,5,7,9...) everything is ok, when the data byte are even (2,4,6,8,...) the slave receive correctly only the first two bytes.
An example: if I send packet:85,1,1,1,0,49 I receive 85,1,1,1,0,49;
if I send 85,2,2,2,0,98, I receive 85,2,127,255,47,32.
With the same even data bytes I receive always the same incorrect packet (is not casual).
So every data odd packet is correctly received, and every even data packet is received incorrectly.
Is there anyone with an idea of this strange behaviour?
Thanks
Elena

*** in the transmitter ***
{...//the packet is pacchetto[]
//rx_tx_int is PIN RC5 (int2), used to generate int on the slave and to send data. I cannot use two different pins
for (i=0;i<3;i++) //I send two bytes at a times, and do a synchronization every couple of bytes
{output_bit(rx_tx_int,1); //with i=0 this generate interrupt on the slave with i=1,2 just only used for synchronization
delay_ms(6); //
output_bit(rx_tx_int,0);//synchronization with the slave
delay_us(10);

for (j=0;j<2;j++)
{tx_byte=pacchetto[2*i+j];
for(cnt=8; cnt > 0; cnt--) // send bit from msb to lsb
{send_bit=bit_test(tx_byte, cnt - 1);
output_bit(rx_tx_int, send_bit);
delay_us(500); }
}
}
}

*** in the receiver ***
{...
for (i=0;i<3;i++)
{while(input(rx_tx_int) != 0) {;}//synchronization with the master
for (j=0;j<2;j++)
{for(cnt=8; cnt > 0; cnt--)
{if(cnt == 8)
{ delay_us(300);
receive_bit=input(rx_tx_int); }
else
{delay_us(500);
receive_bit=input(rx_tx_int);}
if(receive_bit == 1)
{bit_set(rx_byte, cnt - 1); }
else
{bit_clear(rx_byte, cnt - 1); }
}
pacchetto[i*2+j]=rx_byte;
}
}
}

********* Note that the rest of the program is perfect, no error while compiling, no other problem. Interrupts are well handled, when the receiver enter the int routine it disables interrupts and execute the receive procedure. At the end of it re-enable interrupts.

[Ttelmah]

You leave out the most important piece. How is this data being transmitted?. What are the settings at each end?. Your failure looks like what you would expect, if transmission was 7bit at one end, and 8bit at the other.

Best Wishes