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[SOLVED] PIC18F26K83 I2C slave problem
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Ttelmah



Joined: 11 Mar 2010
Posts: 18233

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PostPosted: Sat Apr 16, 2022 2:52 am     Reply with quote

On the CSTR thing, I mentioned this here a while ago.
On a few chips, this won't clear immediately after the data is read. There
has to be a tiny delay. I think it is listed in one erratum, but seems to
actually apply to quite a few chips that don't list is as an errata.
Therefore I recommended that if you had problems, try clearing this.

There is also one other bit that may need handling. GCEN. If this is enabled
you will get an interrupt if a general call occurs on the bus, and the
standard handler will not know what to do in this event.
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