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Josep Robert
Joined: 27 Mar 2018
Posts: 25
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| PIC18LF47K40 - restart_cause() returns unknown values. |
 Posted: Thu Oct 03, 2019 4:12 am |
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Hello!
When I try to use the restart_cause() function I obtain values that are not in the list of constants in 18LF47K40.h file.
Can you help me to obtain the real cause of any restart cause?
I use: PCH Compiler 5.076 and MPLAB X IDE v5.25.
Here a small code to check one of these problems:
| Code: |
#include <18LF47K40.h>
#use delay(clock = 16MHZ, internal)
#FUSES WDT_SW
#FUSES WDT65536
void main()
{
int16 RestartCause;
int8 RChigh, RClow;
RestartCause = restart_cause();
RChigh = make8(RestartCause, 1);
RClow = make8(RestartCause, 0);
write_eeprom(0, RChigh);
delay_ms(1);
write_eeprom(1, RClow);
setup_wdt(WDT_ON);
while(TRUE)
{
//restart_wdt();
delay_ms(1000);
}
}
/*
EE Data Memory
Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ASCII
310000 03 2F FF FF FF FF FF FF FF FF FF FF FF FF FF FF ./...... ........
310010 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ........ ........
0x032F is an unknown restart cause in ccs file 18LF47K40.h:
// Constants returned from RESTART_CAUSE() are:
#define NORMAL_POWER_UP 0x33C
#define BROWNOUT_RESTART 0x33E
#define MCLR_FROM_SLEEP 0x237
#define WDT_TIMEOUT 0x12F
#define WDT_FROM_SLEEP 0x03F
#define INTERRUPT_FROM_SLEEP 0x23F
#define MCLR_FROM_RUN 0x337
#define RESET_INSTRUCTION 0x33B
#define STACK_OVERFLOW 0x3BF
#define STACK_UNDERFLOW 0x37F
#define WDT_WINDOW_VIOLATION 0x31F
*/
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Thank you very much.
Best Regards,
Josep Robert |
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temtronic
Joined: 01 Jul 2010
Posts: 9226
Location: Greensville,Ontario
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| Posted: Thu Oct 03, 2019 7:21 am |
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OK, 'silly' test.
Instead of saving the restart cause to EEPROM and reading it, just print it to PC terminal program.
There 'might' be a problem with the EERPROM writing, reading or the actual EEPROM cell.
Also is 1ms long enough ?
Can that PIC write individual bytes ? Most need to read a block, erase, then write a block...
I'm sure others who use that PIC or family will respond....
Jay |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19510
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| Posted: Thu Oct 03, 2019 12:59 pm |
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Unfortunately this is now common.
On the earlier chips, most restart states had specific patterns of bits.
The CCS function and defines assume this. However on a lot of the newer
chips some of the restart causes have several bit as 'u' (indeterminate),
so the simple equality test that could be applied with the more basic chips
no longer works.
The watchdog reset only guarantees 2 bits to be 0. Every other bit is
indeterminate.
CCS really need a major rethink about these tests for the later chips. |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Re: PIC18LF47K40 - restart_cause() returns unknown values. |
| Posted: Thu Oct 03, 2019 1:21 pm |
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| Josep Robert wrote: |
0x032F is an unknown restart cause in ccs file 18LF47K40.h:
// Constants returned from RESTART_CAUSE() are:
#define NORMAL_POWER_UP 0x33C
#define BROWNOUT_RESTART 0x33E
#define MCLR_FROM_SLEEP 0x237
#define WDT_TIMEOUT 0x12F
#define WDT_FROM_SLEEP 0x03F
#define INTERRUPT_FROM_SLEEP 0x23F
#define MCLR_FROM_RUN 0x337
#define RESET_INSTRUCTION 0x33B
#define STACK_OVERFLOW 0x3BF
#define STACK_UNDERFLOW 0x37F
#define WDT_WINDOW_VIOLATION 0x31F
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The lower 8 bits match, so it's some form of Watchdog reset. |
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benoitstjean
Joined: 30 Oct 2007
Posts: 566
Location: Ottawa, Ontario, Canada
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| Posted: Thu Oct 03, 2019 5:02 pm |
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Haven't looked at that chip but for the PIC24EP, it has an RCON (Reset Control Register) and each bit specifies a reset type as seen below. These (for the PIC24) can be seen in document DS70602B pages 8-5 and 8-6.
Maybe there's a similar document for your device?
bit 15 TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 =An illegal opcode detection, an illegal address mode or an uninitialized W register used as an Address Pointer caused a Reset
0 =An illegal opcode or uninitialized W register Reset has not occurred
bit 13 SBOREN: Software BOR Enable/Disable bit(4)
1 =BOR is turned on in software
0 =BOR is turned off in software
bit 12 Unimplemented: Read as ‘0’
bit 11 VREGSF: Flash Voltage Regulator Stand-by During Sleep bit
1 =Flash voltage regulator is active during Sleep
0 =Flash voltage regulator goes into Stand-by mode during Sleep
bit 10 Unimplemented: Read as ‘0’
bit 9 CM: Configuration Mismatch Flag bit(2)
1 = A configuration mismatch Reset has occurred
0 = A configuration mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Stand-by During Sleep bit
1 =Voltage regulator is active during Sleep
0 =Voltage regulator goes into Stand-by mode during Sleep
bit 7 EXTR: External Reset Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(3)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3 SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset or Power-on Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
The you can probably add some assembly code that reads the register immediately at power-up...
Ben |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19510
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| Posted: Thu Oct 03, 2019 10:40 pm |
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The restart is flagged by the RCON and STATUS registers.
On this chip both return 'indeterminate' for all but two bits on a
watchdog restart. This makes the simple test for equality used by the
CCS system, not work.
Restart_cause inverts bit 8 in the value, So it is a watchdog, if bit 4 of
restart_casue == 0 and bit 8 == 1.
So 0x12F or 0x32F are both watchdog restarts.
As I said CCS need to rethink how this is coded.... |
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benoitstjean
Joined: 30 Oct 2007
Posts: 566
Location: Ottawa, Ontario, Canada
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| Posted: Fri Oct 04, 2019 4:53 am |
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| Ah! Sorry! My mistake. |
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dgi
Joined: 07 Jan 2004
Posts: 11
Location: Philadelphia, USA
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| restart_cause() only returns 8 bits?? |
| Posted: Thu Sep 17, 2020 2:20 pm |
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I'm using PIC18F27Q10 and PCWHD 5.095.
In my program I call restart_cause() to find out what caused the last restart. Right now it is returning 0x2F. The problem is that restart_cause() returns only 8 bits, while the constants in 18F27Q10.h are 12 bits, and the upper bits don't match. Is this a big in the compiler? How do I get the rest of the bits from restart_cause() ?
| Code: |
void hotel_print_powerup_message(void)
{
int16 what_happened = restart_cause();
printf(nmea_txt,"$RESTART,");
if (what_happened == NORMAL_POWER_UP)
printf(nmea_putc,"NORMAL*");
else if (what_happened == RESET_INSTRUCTION)
printf(nmea_putc,"RESET_CMD*");
else if (what_happened == WDT_TIMEOUT)
.. etc..etc... |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19510
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| Posted: Fri Sep 18, 2020 1:03 am |
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That needs to be pointed out to CCS.
It's just a fault with the declaration in the .h file.
It needs to be:
_bif int16 restart_cause(void);
It is correct for many(most) other chips. So (for example) the 27K40,
the 26J11 etc. etc...
If I make this change to the header and save a copy of it (then set the
compiler to use this copy rather than the 'master' stored with the compiler),
it does correctly put stuff into the upper byte of the return value.
So:
| Code: |
#include "18F27Q10.h" //Inverted commas so it uses the local copy
#device ADC=10
#FUSES NOWDT //No Watch Dog Timer
#use delay(crystal=20000000)
void main()
{
int16 val;
val=restart_cause();
//assembly shows stuff being written into the high byte here
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