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PWM-duty cycle problem

 
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iruraz



Joined: 28 Jul 2009
Posts: 10

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PWM-duty cycle problem
PostPosted: Wed Mar 17, 2010 8:43 am     Reply with quote

Hi Everybody,

I try to obtain 120KHz carrier signal with 50% duty cycle. My crystal frequency 7.68MHz.
Code:

setup_timer_2(t2_div_by_16,0,1);

This part of code give 120KHz signal but I couldn't see 50% duty cycle because PR2=0. How can I obtain 50% duty cycle?
Code:

#include <16f877.h>

#fuses XT,NOWDT,NOPROTECT,NOBROWNOUT,NOLVP,NOPUT,NOWRT,NODEBUG,NOCPD

#use delay (clock=7680000)

#use fast_io(c)

void main()
{
   setup_psp(PSP_DISABLED);        // PSP birimi devre dışı
   setup_spi(SPI_SS_DISABLED);     // SPI birimi devre dışı
   setup_timer_1(T1_DISABLED);     // T1 zamanlayıcısı devre dışı
   setup_adc_ports(NO_ANALOGS);    // ANALOG giriş yok
   setup_adc(ADC_OFF);             // ADC birimi devre dışı
   
   set_tris_c(0x00);
   
   setup_ccp1(ccp_pwm);
   
   setup_timer_2(t2_div_by_16,0,1);
   
   while(1);
}

Regards.
meereck



Joined: 09 Nov 2006
Posts: 173

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PostPosted: Wed Mar 17, 2010 9:07 am     Reply with quote

according to my calculations:
Code:
setup_timer_2(t2_div_by_1,15,1);
set_pwm1_duty(8);
iruraz



Joined: 28 Jul 2009
Posts: 10

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PostPosted: Wed Mar 17, 2010 12:10 pm     Reply with quote

Thanks @meereck. I tried and obtained. Product result is same but what is the difference between
Code:
setup_timer_2(t2_div_by_1,15,1);

and
Code:
setup_timer_2(t2_div_by_16,0,1);

?
Ttelmah



Joined: 11 Mar 2010
Posts: 19348

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Ttelmah
PostPosted: Wed Mar 17, 2010 4:00 pm     Reply with quote

You are setting the prescaler to 16.
You can't basically divide 'counts' taking place in the prescaler, only ones taking place in the actual PWM counter (thought further note below here...).
The counter in Meerek's version, is counting to 16 and resetting (always PR2+1), so you can then set the duty to half this value to get 50%.

Using the prescaler, the main counter, is just counting 0,1,0,1, so you can either get off, or full on, not a 50% duty cycle...

However, the actual 'counter', is 2 bits longer than the PR2 register. These extra bits would potentially allow a 50% duty cycle, using:

setup_timer_2(t2_div_by_16,0,1);
set_pwm_duty(2L);

Using a 'long' value, tells the compiler to access the extra bits. Effectively accessing 1/4 'count' steps.

Best Wishes
iruraz



Joined: 28 Jul 2009
Posts: 10

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PostPosted: Thu Mar 18, 2010 2:10 pm     Reply with quote

Thanks @Ttelmah .
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