PWM-duty cycle problem

iruraz · Joined: 28 Jul 2009 Posts: 10

Hi Everybody,

I try to obtain 120KHz carrier signal with 50% duty cycle. My crystal frequency 7.68MHz.

meereck · Joined: 09 Nov 2006 Posts: 173

according to my calculations:

iruraz · Joined: 28 Jul 2009 Posts: 10

Thanks @meereck. I tried and obtained. Product result is same but what is the difference between

Ttelmah · Joined: 11 Mar 2010 Posts: 19510

You are setting the prescaler to 16.
You can't basically divide 'counts' taking place in the prescaler, only ones taking place in the actual PWM counter (thought further note below here...).
The counter in Meerek's version, is counting to 16 and resetting (always PR2+1), so you can then set the duty to half this value to get 50%.

Using the prescaler, the main counter, is just counting 0,1,0,1, so you can either get off, or full on, not a 50% duty cycle...

However, the actual 'counter', is 2 bits longer than the PR2 register. These extra bits would potentially allow a 50% duty cycle, using:

setup_timer_2(t2_div_by_16,0,1);
set_pwm_duty(2L);

Using a 'long' value, tells the compiler to access the extra bits. Effectively accessing 1/4 'count' steps.

Best Wishes

iruraz · Joined: 28 Jul 2009 Posts: 10

Thanks @Ttelmah .