SPI bus as a slave on the PIC chip

[abq_guy]

Hello,

I am using the PIC18F8722. It is connected to an FPGA on one of the SPI bus and to a DAC and ADC on the other SPI bus. The SPI bus connected to the DAC and ADC will be configured as a MASTER, whereas the SPI bus connected to the FPGA is configured as a SLAVE.

The FPGA will initiate requests for setting the voltage on the DAC and reading back from the ADC.

In the Slave mode, the PIC cannot initiate the data transfer to the FPGA. My question is that how will it send the ADC data to the FPGA if it cannot initiate them ?
Also I want to read the data every 100ms from the ADC.
The user can also set the DAC at anytime he wishes. If the data from the ADC is being read while the user wants to set the voltage on the DAC, will it cause collisions on the SPI bus ?

This is more of an system architecture problem. Please elaborate.

Thanks,

abq_guy

[Ttelmah]

The first part is down to you designing a signal. Typically, use an output line that signals the master device to say that the slave has data ready, and triggers it to initiate a transaction.
The second, is down to using buffering. Obviously there can only be one transaction on the bus at a time, but the speed of a typical SPI transaction, will be a few uSec. You buffer the request to set the DAC, and send it as soon as the ADC reading has completed. A delay of a few uSec.

Best Wishes

[abq_guy]

[Ttelmah]

SPI, is full duplex. Data is transferred both ways at the same time. _But_ unlike RS232, one device has to control all transactions (establishing the clock). This is the master.
It is the PIC (the master for the two external devices), that will have to buffer the DAC value. These devices will presumably have slave select lines implemented (will be needed to say which device to talk to), and if the master is talking to the ADC, it'll have to complete these transaction, _then_ deselect this chip, and select the other, then send the DAC request.
Only masters can initiates transactions (start the clock).
If a user is sending a request, who is generating the clock (FPGA?). If so, how is this told to do so?. If the FPGA is the master, then it'll control the timings, and access. If it has more than one device on any single bus, and their operation is asynchronous to each other, then there either has to be buffering fo the requests, or the one request has to be delayed till the bus is clear.
You really can't transfer data from different devices at the same time. Each device will require a 'frame' of some form (select line dropping, command being sent, reply etc.), and to have another device sending data at the same time, and not leading to conflicts, would require complete control of the nature of the packets, getting them to be the same size etc., and triggering the transfers using the same control (or sync can be lost).
SPI, is full duplex, but is 'point to point' only one pair of devices talking at any one time.

Best Wishes