Watchdog reset, effect on I/O pin & ZERO_FILL

[cparsons]

compiler version: PCWH V4.070

I'm using one of the port D PIC18F4580 pins to control the active-low reset line of another peripheral.

In the case that the PIC resets due to a watchdog timeout I don't want the other peripheral also being reset - I'd like the pin to stay high.

The details of the PIC register values after a soft reset seem to indicate the Port D pins will be unchanged.

If I look at the pin with scope during a watchdog reset I see the pin voltage dip down to 1.9V over a period of 200us before going back up to the 3.3V, the high voltage.

If I create a much smaller program that configures a few registers then causes a watchdog reset then the voltage dip is of the order of a few microvolts over 15us.

If I compare the two .lst files I see that the larger program has about 500 CLRF instructions before the main() function instructions, presumably clearing memory and registers. The smaller program uses much less RAM so only has a couple of CLRF instructions before main().

I've read the documentation, and see the #ZERO_FILL compiler directive. I can't find anywhere in my code where I have included this directive, nor can I find an option for it in the IDE.

- Can anyone see why the CLRF instructions would have a bearing on the pin during a reset?
- If not, are there any other factors that influence the voltage on the pin through a reset?
- Is ZERO_FILL enabled by default on some versions of the compiler? If so, is there a way to turn it off?

Thank you

Chris Parsons

Here is the first instructions of the short program with the very ouput pin voltage dip:

[PCM programmer]

If you have global variables and you declare them as 'static', then
the compiler will clear them.

The CCS manual says: