Problem with PWM Duty Cycle

pklein · Joined: 14 Nov 2007 Posts: 7

Hi,

I cannot get a 10 bit pwm duty cycle. When I put a number that is higher than 8 bit into the duty cycle I get full pwm duty.

This is my code:

setup_ccp2(CCP_PWM);
setup_timer_2(T2_DIV_BY_1, 63, 1);
set_pwm2_duty((int16)255);

I can only vary pwm in the 8 bit range. Is there something else I need to change. Im using a 16F917

Thanks

PCM programmer · Joined: 06 Sep 2003 Posts: 21708

I compiled the following test program with vs. 4.064 and it worked in
10-bit pwm mode. Your test value for duty cycle is very close to 100%,
so all you will see on the oscilloscope is a very thin negative pulse.

I put in the following duty cycle values, and measured the pulse width
on an oscilloscope. Since I'm using a 20 MHz crystal, the clock period
is 50 ns, and the pulse width does change in 50 ns increments, which
is correct for 10-bit PWM operation.

Ttelmah · Guest

The key is the setup timer statement.
The PWM range, is a maximum of 10bits, also limited to 4* the timer maximum count+1. With a timer setup of 63, the PWM limit, is 4*64. To get a full 10bit PWM, the timer setup has to increase to 255. With the example given, and 63 in the timer, you will get 255:256 on, with just a single 50nSec low pulse.

Best Wishes

pklein · Joined: 14 Nov 2007 Posts: 7

Thanks. That makes perfect sense. I didnt know about it being limited to 4 times the timer count.

Ttelmah · Guest

On most PICs, there is to be a table in the data sheets, giving the 'effective' PWM resolution, with different timing setups. This seems to have disappeared from a few of the latest PIC sheets, but if you pull one of the older ones (for example, the one for the 16F684), then table 11-4, gives "example pwm frequencies and resolution", with the output frequency, and the 'effective resolution' in bits on the bottom line.

Best Wishes