DEFINES for spi_setup

[theteaman]

Hello

I have searched through this board but am unable to know just what the 'SPI_CLK_DIV_*' definitions mean when dealing with SETUP_SPI(). I have a FLASH module that can run at either 20 or 50MHZ. My PIC currently uses a 40MHz crystal. What parameter should I be using to setup_spi()? Thanks

[PCM programmer]

The constants in the CCS ".H" files for the PICs will usually be
abbreviations for settings that are explained in the PIC data sheet.
Look in the SPI section of the 18F452 data sheet. It says this:

[theteaman]

[PCM programmer]

The answer is in the data sheet:

[theteaman]

Thanks PCM Programmer

1 more question.. speaking of SPI at 10MHz. I'll actually be sending data from a 5V PIC to a 3.3V module. If I use a zener diode, would you say that the capacitance of the zener would be too high for such a high frequency? Would I be better suited to just use a voltage divider with say, a 120ohm and 220ohm resistor?

many thanks

[PCM programmer]

The capacitance would be too high with a Zener diode. The rise time
would be too long. You only have a 100 ns period at 10 MHz.

Your proposed voltage divider with 330 ohms total resistance to ground
is a little stiff. At a 5v nominal Voh, that's a 15 ma load on the pin.
You would need three of those, for SDO, SCK, and \CS. You should
probably use higher values for the resistors.

This thread has other proposals:
http://www.ccsinfo.com/forum/viewtopic.php?t=26522

I would use 74HCT and 74LVC buffers as level translators, as described
in this thread:
http://www.ccsinfo.com/forum/viewtopic.php?t=23154

There's another problem. I looked in the 18F452 data sheet at the
SPI master timing, at this section:
FIGURE 22-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
It shows that setup and hold time for incoming data on the SDI pin
is 100 ns each. That amounts to a 5 MHz maximum clock frequency.
That assumes that the MMC card has no delay in outputting data.
But it will have some delay. I don't know what it is, you'll have to
look it up in the spec, but your real maximum SPI clock freq might
only be 4 MHz.

[theteaman]

PCM programmer: you have been of great help. Thank you.

I dont think I need a level translator for 3.3V to 5V PIC pulses though, as the minimum VIH is lower than 3.3V anyway.. ??

Anyway thanks, i will use higher resistor values and keep an eye on the current

[Ttelmah]

What you have to consider is that 'VOh', of the 3.3v chip, won't be 3.3v. Odd's are, that it'll be something like 2.6v. The 5v logic input, is not guaranteed at this voltage to see a '1'. You may well 'get away', with a pull up resistor on the 3.3v output pin, running to +5v, and a clamp diode from the same point, to the 3.3v rail, but for reliable operation, especially at high speed, a proper buffer is much more likely to work. There are chips that contain a couple of pairs of level translators in one package, which would do both required translations in one IC.

Best Wishes

[theteaman]

Ttelmah: you are right, thanks. i am now convinced to just use an 18LF at 3.3V.... and get rid of all this wasted power!

[ckielstra]

[theteaman]

[ckielstra]

[theteaman]

[ckielstra]

You can find these figures in the chapter 'Electrical Characteristics'. Using the 4xPLL circuit is only a change in the way you are generating the system clock, it doesn't relate to the maximum allowed clock frequency at a certain voltage.
Details are different between PIC families, which processor model are you using?

[theteaman]