8080 protocol bus

[jccsantos]

Hi, with the signals CS# , RW#, RD# , D/C# , RST# and data bus (8 bits), and a pic18f452, what is the right sequence for start a 8080 bus sequence,
like what´s first cs->dc->rw->data or else......

And for a correct port inicialization on pic18f452, (planned to use portC for signal´s and portD for bus), assign each signal to a port (byte portsign.....
cs = portsign.0 and so on, or make a struct.)




Thank´s in advance.

[Ttelmah]

Er. What '8080'...
The signal names you have, don't agree with the lines on the 8080 microprocessor, or the control chip for that processor (the 8228). So, are you talking some proprietary bus (like the IMSAI 8080 interface)....
/RST, sounds like the PCI bus.
You need to give us some 'clues'....

Best Wishes

[jccsantos]

sorry,

Is for oled controller from densitron DD-32645C-2A, The interface can be 6800-parallel interface , 8080-parallel interface or SPI, but in this case, densitron have make de 8080-parallel interface the only interface available, and my doubt resides here: the sequence of signal´s.

The signal´s of controller are all active low.
CS - chip select
rw - Write data
rd - read data
D/C - data or commands
RST - Reset device

D0....D7 - data bus

The display controller is a an ssd1303.

And one more thing, for use with an pic18f452(in this case) or another pic,
for config the port´s (in this case PortC for signal´s and PortD for data) make a struct like lcd.c example or like the nokia3310 port assigment?

Note: Unable to explain better because I can´t write fluent English.(google translator).

[treitmey]

[Ttelmah]

Hm.
Their pinout, is not really anything much to do with the 8080. It is semi compatible, with a decoded I/O port on the 8080...
First comment, have you got the data sheet?. If not, you will need it, since it describes the commands, and this has the order of the operations shown on page 10.

D/C, is data/low control. This is set _first_, to say whether transaction is data, or a control byte.
WR, or RD, is then dropped to say that the transaction is either a read, or a write.
Then CS is dropped.
If you are writing, you then apply the data, and then at least 40nSec latter, raise the CS. The data is latched at this point.
If you are writing, wait at least 140nSec, from dropping CS, and then read the data, and raise CS (the data is held for 20nSec after the rising edge of CS).
Remember you will have to set the tris on the port you are using to access the data, so it is set as input, _before_ you drop the RD line.
The rst line, should be dropped, and then raised, when the device is first turned on, to reset it.

Best Wishes