SPI Slave Receiving byte is shifting

[buneri]

Hi All,
I am using two PIC 16f87A chip for SPI communication.
Using PCWH 4.020

The master work fine, but the slave receiving the data with byte shifting.
Actually i wanna transfer four bytes of data at a time and simultaneously to receive by the slave in the same order.
But the slave receiving the data, with shifting of bytes not in the same order but the order of byte is changing contnuously.
Plz tell me wat i m doing wrong? Here is the coding of spi slave which i have used for receiving the data in order:

setup_sp(SPI_SLAVE|SPI_SS_DISABLED|SPI_MODE_0_1|SPI_CLK_DIV_16);

while(1)
{
while(!spi_data_is_in());
spi[i]=spi_read(0);
i++;

if(i==4)
{
data[0] = make16(spi[1],spi[0]);
data[1] = make16(spi[3],spi[2]);

hold_regs[0]=data[0];
hold_regs[1]=data[1];

//After that transfer it to the modbus master since its also modbus slave

}

for master
setup_spi(SPI_MASTER | SPI_MODE_0_0 |SPI_MODE_0_1| SPI_CLK_DIV_16);

Thanks

[ckielstra]

Your slave:

[buneri]

Thanks for your response.
I have change the Mode of slave as per your advise. i.e, both master and slave now have Mode 0-1 .Now

setup_spi(SPI_SLAVE|SPI_SS_DISABLED|SPI_MODE_1_0

But the problem still there! bytes are same as transmitting but not receiving in the specific order

can u tell me plz wats the role of CKE in selecting modes, whats the method of selecting of suitable Mode and clock speed for SPI.

Thank You

[ckielstra]

[buneri]

Dear Sir,
One thing i want to clearifying that is,
I am using SPI slave for just reading then,

for(i=0; i<4; i++)
data[i]=spi_read();
FL=make32(data[2],data[3],data[0],data[1]);

Is the above coding is correct for SPI?

Thanks

[ckielstra]

[buneri]

Dear Sir,
Master Code with Chip Selec disabled

setup_spi(SPI_MASTER | SPI_MODE_1_0 | SPI_CLK_DIV_4);
setup_timer_1(T1_INTERNAL|T1_DIV_BY_8);

enable_interrupts(INT_TIMER1);
enable_interrupts(GLOBAL);

modbus_init();

//////////////////////////// While Loop /////////////////////////

while(1)
{
if(input(CS)
{
for(i=1; i<5; i++)
spi_write(reg_arayip1[i]);
}

CS is the synchronized bit from SPI slave for starting communication
because i need it for other task from slave to finish first

It works fine now but very rarely distrub the other tasks of SPI master

Thanks

[Neutone]