ADC conversion timing

[oxxyfx]

Hello,

I am quoting off the datasheet of the 16F506 I am planning to use for AD conversion:

"the ADC has 4 clock source settings ADCS<1:0>. There are 3 divisor values 16, 8 and 4. The fourth setting is INTOSC with a divisor of 4."

Also:

"The ADC requires 13 Tad periods to complete a conversion. The divisor values do not affect the number of the Tad periods required to perform a conversion. The divisor values determine the lenght of the Tad period."

I will be running this chip at 4Mhz internal oscillator. In this case, how long will a conversion take? I am not sure how to calculate this.

Thanks, Oxy.

[Ttelmah]

If you read on in the data sheet, you will find that the internal RC oscillator, is not recommended without quite a few caveats. There is a minimum spec for Tad (2uSec), so you take the divisor that gives the next value matching this, or above it. For 4MHz, /8, gives 2uSec. Then the conversion takes 26uSec.

Best Wishes

[oxxyfx]

Thank you Ttelmah,

Looking a little deeper into the datasheet, on page 54 I found a table 9-2 which specifies the Tad timings based on various oscillators. I should have looked before I posted... However this still leaves one question - you say the internal oscillator is not recomanded, however the datasheet states:
"If analog input is desired at these frequencies, use INTOSC/4 for the ADC clock source."

Then in the table for the INTOSC at 8Mhz Tad=0.5us and at 4Mhz=1us. Also these 2 are not shaded, that means it would give us accurate conversions.

Sorry for the doubts, but which one is true now?

[Ttelmah]

OK.
Tad, on the 16F506, (with only an 8bit ADC), is allowed to go as low as 500nSec. Earlier chips had a limit at 2uSec for this, as do most with 10bit ADC's. So /4, is fine on this chip, but would not be OK on most chips.
_However_, the comment about IntRC remains. The data sheet itself, doesn't carry the warnings about this, but the 'family' sheet, which gives general notes about things, suggests that IntRC, is only used, if a sleep conversion is performed (stopping the rest of the chip while the conversion takes place). This though is generally talking about the 10bit ADC's, rather than the 8bit version. The reason, is that if you use the RC oscillator, the conversion is asynchronous to other things on the chip, so you tend to get more variation from whatever else is going on on the chip, than from using the synchronous clock. On the 10bit converters this is important, and often mentioned in the individual data sheets, but on this small chip (few peripherals, and only 8bit accuracy on the ADC), together with a much more stable internal oscillator, than on most older chips), the results may well be acceptable. Hence, as I say, there are 'caveats' about using IntRC. However, it may well be acceptable, depending on what accuracy you want (and gives a faster conversion)...
Remember separately though, that the limit on how fast you can 'sample', is dependant on how quickly the internal sample capacitor, can 'match' the voltage being presented after the conversion completes. When the conversion takes place, the capacitor is disconnected from the external signal, then when the conversion completes, the internal capacitor starts charging to match the external voltage. Hence the sequence has to be:

Select input (if applicable)
1)
Wait for the internal capacitor to reach the input voltage
Take the reading.
Loop back to '1'.

Now on most chips, the input capacitor value is specified, but on this one it isn't. The input up to the capacitor, is shown in the comparator section, but the actual sampling capacitor value is missing from the data sheet...

Best Wishes

[oxxyfx]

Thank you for the detailed explanation, it is all clear now. Sorry I have to be such a doubting person, but one has to learn these things somehow. I personally cannot build anything if I don't understand how is working and what's the theory behind it.

Thank you again.