CCS internal_eeprom.c routines

[MarcosAmbrose]

I'm just looking at the CCS internal_eeprom.c file and there's something I don't understand. Whenever I'm writing several bytes of data to the internal EEprom I set a flag then wait for the INT_EEPROM interrupt before writting the next byte. It appears to take several milli secs between writes.

On the other hand, the CCS routines in the internal_eeprom.c file don't even have a time delay between writes and they appear to just blasting data at the EEprom in a FOR loop.

Can someone explain to me how the CCS routines work when I know it take longer to write a byte

[Ttelmah]

Their own 'write_eeprom' code, tests for the write to complete internally.
If you look at the code generated, for the command:

WRITE_EEPROM(addr+count,ptr[count]);

Ignore all the stuff 'loading' the data bytes, you get to:

1750: MOVWF FA7
1752: BSF FA6.1
1754: BTFSC FA6.1
1756: BRA 1754
1758: BCF FA6.2
175A: MOVF 00,W
175C: IORWF FF2,F

Notice the third, and fourth lines, where it sets the 'write' bit in EECON1, and then waits for it to clear. If you read the data sheet about this bit, it says:
" Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) "
So, they are waiting for this bit to clear which implies the operation has completed.

Best Wishes

[MarcosAmbrose]