SPI CDP68HC68P1 problem

[SherpaDoug]

Has anyone used a SPI 8 bit I/O port the CDP68HC68? I guess it was popular with the 68HC05 series processors, but is now hard to find. We have a large quantity and at least some are defective so I volunteered to build a little PIC screener to test them. But the Intersil data sheet is really vague on which edges data should be clocked in on and how to set port direction. I have tried to use "standard" SPI timing but none of the chips are working with that.

If someone has PIC code that drives this chip, or even a decent datasheet I would be very grateful.
_________________
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[PCM programmer]

This page shows the sample edge and clock idle states of the
four SPI modes:
http://www.totalphase.com/support/articles/article03/#modes

Here is the Intersil chip's data sheet:
http://www.intersil.com/data/fn/fn1858.pdf
On page 7, in the 2nd paragraph on the left side, it says the SPI mode
is selected by the state of the SCK signal when \CS goes low.
This can be seen in Figure 6, at the bottom of page 6.
For example, if you initialize the SCK pin to a low level at the start
of an SPI operation, then when you take \CS low, the Intersil chip
will be be operating in SPI mode 1.

See my post in this thread for information on setting up SPI mode 1.
http://www.ccsinfo.com/forum/viewtopic.php?t=29656

Also note that at 3.3v operation (of the Intersil chip), your max SCK
clock frequency is only 1 MHz. Make sure you use the correct divisor
in your setup_spi() statement to reflect this limitation.