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turbo2ltr
Joined: 27 Jan 2005 Posts: 12
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CCP1 on 16F690 bug? |
Posted: Fri Jan 26, 2007 3:09 pm |
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I'm trying to figure out why my CCP is not generating interrupts. I look at the dissasembly and find this:
Code: | 223: setup_ccp1(CCP_CAPTURE_FE); // capture falling edge
09D 1283 BCF 0x3, 0x5
09E 0197 CLRF 0x17
09F 3004 MOVLW 0x4
0A0 0097 MOVWF 0x17
0A1 0197 CLRF 0x17
0A2 0196 CLRF 0x16 |
I would assume that the two CLRFs are supposed to clear the high and low capture registers (0x15,0x16), but instead it's clearing the CCPM control register (0x17) after it just set it up.
The header file has this:
Code: | long CCP_1;
#byte CCP_1 = 0x15
#byte CCP_1_LOW= 0x15
#byte CCP_1_HIGH= 0x16 |
So it appears correct.
So is this a compiler bug?
TIA.
Mike |
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PCM programmer
Joined: 06 Sep 2003 Posts: 21708
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Posted: Fri Jan 26, 2007 3:44 pm |
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Post your compiler version. |
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turbo2ltr
Joined: 27 Jan 2005 Posts: 12
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Posted: Fri Jan 26, 2007 3:57 pm |
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CCS PCM C Compiler, Version 3.227 |
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turbo2ltr
Joined: 27 Jan 2005 Posts: 12
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Posted: Fri Jan 26, 2007 3:58 pm |
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Code works great if you replace the setup_cpp1 with the asm is creates, sans the error. |
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PCM programmer
Joined: 06 Sep 2003 Posts: 21708
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Posted: Fri Jan 26, 2007 5:23 pm |
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Here's the code generated for the 16F690 with PCM vs. 3.249.
Comments added.
Code: |
.................... setup_ccp1(CCP_CAPTURE_FE);
001B: BSF 03.5 // Bank 1
001C: BSF 07.5 // TRISC.5 = input (CCP1 pin)
001D: BCF 03.5 // Bank 0
001E: CLRF 17 // CCP1CON = 0x00
001F: MOVLW 04
0020: MOVWF 17 // CCP1CON = 0x04
0021: CLRF 1C // PWM1CON = 0x00
0022: CLRF 1D // ECCPAS = 0x00
0023: BTFSS 12.2 // Is Timer2 on ?
0024: GOTO 028 // If not, skip next code
0025: BCF 0C.1 // Set TMR2IF flag = 0
0026: BTFSS 0C.1 // Then wait until TMR2IF = 1
0027: GOTO 026
0028: BSF 03.5 // Bank 1
0029: BSF 07.5 // TRISC.5 = input
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You could write C source code to do the same thing.
Use #byte and #bit statements to define the register
addresses and write your own function called my_setup_ccp1(). |
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