clock stretching

[Guest]

I am using a PIC18F2520 as a slave device.
I have a situation where the Master sends the first byte for address match with the R/W bit=0; And then sends the a second byte with R/W bit =1.

I have an infinite loop in my main method, and do not want to get into the I2C interrupt with the master until I have the required data packet for the master ready. So I wanted to the master to wait till I get the data ready for it, before entering the interrupt.

I tried to implement clock stretching by setting the SEN bit. But I faced the following problem.

The master sends the first byte as: 0x5C
The master sends the second byte as: 0x5D

I want the clock stretching to work in such a way, that it keeps the 0x9C in the SSPBUF. And after I enter the I2C ISR, I want to read the SSPBUF (which should have 0x9C waiting for me), and then let the second byte (0x9D) enter the SSPBUF.
Currently I am noticing that in spite of my implementing the clock stretching, by the time I reach the I2C ISR, I notice that the second byte from the master 0x9D has already replaced 0x9C.
If clock stretching wont allow me to do this, any suggestions of other methods to implement this.
I would appreciate the help.

[PCM programmer]

I think the reason you're not getting any replies is because your post
is not clear. At first, you're talking about sending bytes 0x5C and 0x5D.
Then suddenly you start talking about 0x9C and 0x9D. What is the
meaning of this ?

What is the i2c master chip ? Is this a PIC, running a program that
you created, or is it a chip from a manufacturer such as National
Semiconductor, or Maxim, etc. ?

What is the i2c protocol used by the master PIC ? (ie., the sequence
of commands and data used by the Master to communicate with the
Slave device). Did you invent the protocol ?

To get an answer to your question, you have to give a complete
description of the i2c chips (master and slave) and the protocol.