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johnwan Guest
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about multiple of #USE RS232 |
Posted: Tue Jul 29, 2003 6:32 am |
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Dear friend:
I'm use 18F452,
and I have two #use rs232.
I set them at the ISR.
>>//========== UART Define =======================
>>// Hardwave Uart Define
>>#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
>>#INT_RDA
>>function{//get one byte per time}
>>// Softwave Uart Define
>>#use rs232(baud=4800, xmit=PIN_C1, rcv=PIN_A4)
In the normal status is use the Softwave.
At the same time ,
I have TIMER0(25ms),I2C(2Sec,2bytes at two times).
But have some problem,
1.the second rs232 is use in main() like
while(1){...;...;if(kbhit()) {variable=getc();...;};...;}
But there are some string is wrong.
2.have anyone can help to understand the second rs232 ,
how does it work?
Thanks for your visit.
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This message was ported from CCS's old forum
Original Post ID: 144516465 |
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R.J.Hamlett Guest
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Re: about multiple of #USE RS232 |
Posted: Tue Jul 29, 2003 8:20 am |
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:=Dear friend:
:=
:=I'm use 18F452,
:=and I have two #use rs232.
:=
:=I set them at the ISR.
:=>>//========== UART Define =======================
:=>>// Hardwave Uart Define
:=>>#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
:=>>#INT_RDA
:=>>function{//get one byte per time}
:=>>// Softwave Uart Define
:=>>#use rs232(baud=4800, xmit=PIN_C1, rcv=PIN_A4)
:=
:=In the normal status is use the Softwave.
:=At the same time ,
:=I have TIMER0(25ms),I2C(2Sec,2bytes at two times).
:=
:=But have some problem,
:= 1.the second rs232 is use in main() like
:= while(1){...;...;if(kbhit()) {variable=getc();...;};...;}
:= But there are some string is wrong.
:= 2.have anyone can help to understand the second rs232 ,
:= how does it work?
:=
:=Thanks for your visit.
First, why not use streams...
This allows you to give a 'name' to each RS232 routine, and send data to the different routines by adding this name to the output routines. It makes it much easier to see which routine is in use at a particular location. Since you mention using a '18' family chip, this implies you have a fairly late compiler, which will probably support this.
That having been said, your problem is probably timing. The 'soft' UART, depends for it's timing, on the assumption, that nothing else will interupt it. It is possible to get away, with some breaks, but the general 'rule', is that comm timings should be within about 4\% of the required time (this can be stretched a little, if the other end is known to be accurate, since it is the 'total' error from both ends that matters). Now at 4800bps, a bit, is 0.2mSec in length, and a 4\% error, would correspond to just 8uSec. You don't say what clock rate your processor is running, but the interrupt overhead from saving the required registers, is normally about 30-40 machine cycles, plus the time inside the routine, which even assuming you are running at the fastest clock rates available, will be enough to cause timing problems on the soft UART...
You can do a UART simulation for this sort of baud rate, by using one of the programmable timers, and detecting the incoming leading edge (by connecting it to a pin with interrupt abilities), then using the timer, to interrupt you at each 'sampling' point. Since the timer keeps running in hardware, even if another interrupt occurs, it should prevent the errors from being 'cumulative'.
Unfortunately, to use the second RS232, without the data errors, really requires you to disable the interrupt sources, while data is being received.
Best Wishes
___________________________
This message was ported from CCS's old forum
Original Post ID: 144516468 |
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johnwan Guest
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Re: about multiple of #USE RS232 |
Posted: Tue Jul 29, 2003 8:34 pm |
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Thank you very much.
Is it mean any ISR will cause the ERROR?
___________________________
This message was ported from CCS's old forum
Original Post ID: 144516486 |
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R.J.Hamlett Guest
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Re: about multiple of #USE RS232 |
Posted: Wed Jul 30, 2003 2:27 am |
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:=Thank you very much.
:=
:=Is it mean any ISR will cause the ERROR?
It depends on the processor clock rate, the bit rate involved, and the duration spent in the ISR.
So (for instance), if you have a processor at 40MHz (10MIPS), and are running at 2400bps, the timings need to fluctate by no more than perhaps 166uSec, in the entire character (to have any hope at all of the data being recognised/recognisable). Now the interrupt 'overhead' (the time taken to save the registers, and retrieve them), is perhaps 20uSec at this sort of clock rate, so if the interrupt handler itself, only took 15uSec, and the interrupt repeated only at 1/100th sec intervals, this should work (only a 35usec 'worst case' error on the character). However (conversely), the same bit rate, using an 8MHz clock, with the same interrupt, would now find the character timing changing by 175uSec, and the chances of reliable communication are low. Running at double the bit rate, halves the allowable error times, so at 9600bps, even the fast processor, would run into problems...
The allowable error, would also change depending on how accurate the baud rate is at the other end (if for instance this is allready running 1\% 'fast', this reduces how much 'slow' the second chip can run before data errors occur).
Best Wishes
___________________________
This message was ported from CCS's old forum
Original Post ID: 144516489 |
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