SPI porblem while migration from PIC18F252 to PIC18F2525

[maozaohad]

I'm using a system , where the PIC is connected to a TI DSP, and have tried to migrate my code from PIC18F252 to PIC18F2525. the PIC is working in SPI slave mode and the TI is the master.
I have a problem , where msgs sent from the PIC to the TI , are received correctly , and all the msgs from the TI DSP to the PIC are received with errors. I haven't made any changes with the TI DSP.
I've tried connecting CCS support a few times , and they couldn't help me.

my SPI_Enable routine looks like :
void SpiEnable()
{
DDR_OUT(SPI_DOUT);
DDR_IN(SPI_CLK);
DDR_IN(SPI_DIN);
setup_spi(SPI_SLAVE|SPI_L_TO_H|SPI_CLK_DIV_4);
}



where DDR_IN/DDR_OUT are defined as
#define DDR_IN(x) bit_set(*(x/8 + 0x12), x%8) //GPIO
#define DDR_OUT(x) bit_clear(*(x/8 + 0x12), x%8)
#define SPI_CLK PIN_C3
#define SPI_DIN PIN_C4
#define SPI_DOUT PIN_C5


Which will simply set the relevent bit in the relevent register.

any ideas ?

[PCM programmer]

The setup_spi() function sets the proper TRIS. You don't need to add
lines of code to do it. I checked the generated ASM code for PCH vs.
3.249 and it is correct.

[maozaohad]

10x, for your answer.
Things are still not working , here is some more info
* I've compared all the registers from PIC252 and PIC2525 , same registers use the same address on the 252 and 2525 , along with bit allocation inside the registers(besides extra registers that are added in the 2525)
* I've noticed that I'm doing extra work , by setting the bits manually , but I've checked the influence on the registers , and all is OK
I'm working in a slave mode , in the following mode of operation
* Master sends data - Slave send summy data
*Master sends dummy data - Slave sends data , as mentioned in paragraphe 17.3.4 in the PIC18F252 Data sheet.
The clock idle state is low '0'
both master and slave change the data pin while clock change its state from low (idle) to high (active) , so the other device samples the data whenc clk chage its state from high to low - I've verified this using a scope
What is very odd , is that when using the correct mode which is
setup_spi(SPI_SLAVE|SPI_L_TO_H|SPI_CLK_DIV_4) , with or withut SPI_SS_DIABLED , data is received correctly at the master side , and while the master transmits the data correctly (verified on the scope) , data is not recieved at the slave.

When I'm doing something which is totally wrong , and that is conifguring the port with
setup_spi(SPI_SLAVE|SPI_H_TO_L|SPI_CLK_DIV_4 | SPI_SAMPLE_AT_END | SPI_SS_DISABLED );
which will config sspstat.bit6 (CKE) to be 1 - which is wrong , and moreve rwill config sspstat.bit7 (SMP) to be 1 - which is wrong - "SMP must be cleared when SPI is used is Slave mode" section 17.3.1 in the data sheet
In this configuration - Data is received correctly at the slave sides , and the slave sends garbeage to the master.


All reading and writing is done via #int_ssp ISR
Do you have any ideas ?