what activates the PSP interupt?

[zachavm]

I would like to know what activates the PSP interupt. Is is CS going low? Is is WR going low? does it have something to do with the data on the pins?

Zach

[ckielstra]

The easy answer would be: RTFM...

You didn't tell us which processor you are using, but as most PIC processors are using the same basic principles I had a look at the PIC18F458 datasheet. Figure 10-2 and 10-3 tell me the PSP interrupt is triggered by:
- the WR line going inactive at writing.
- The RD line going inactive at reading.

When you would have had a look at the datasheet yourself you would have had an answer even faster than the time it took me to write the answer down.

[rberek]

More specifically, the CS line going high will also trigger PSPIF, but it is unlikely the CS would deassert before ether the WR or RD signals.

[Mark]

[zachavm]

I did look at the data sheet, but this is my first semester using PICs and I am still learning. Thanks for the help.

Zach