Ttelmah Guest
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Posted: Thu Mar 09, 2006 3:39 am |
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You have to define the ADC clock yourself. It is divided _from_ the master clock (or runs from an internal RC clock). The latter tends to perform less well than dividing it from the master clock, especially at higher clock rates (you get asynchronous 'noise' from the master clock - hence it is not recommended for use above 1MHz, except if you put the chip to sleep for the conversion - this is the 'quietest' mode of all). You select the ADC clock, with the 'setup_adc' command.
For the 20MHz clock, setup_adc(ADC_CLOCK_DIV_32), will give an ADC clock at 1.6uSec/bit (625KHz). For 4MHz, setup_adc(ADC_CLOCK_DIV_8), will give an ADC clock at 2uSec/bit (500KHz). Both are inside the required rate, and results should be basically indistinguishable, provided the source meets the specifications on impedance etc..
Best Wishes |
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