Quick question about the ASM output.

[neil]

I'm sure there will be a valid reason, but can anyone explain why the ASM generated by CCS uses 'F' instead of 0 or 1 for the second field for some opcodes? The Microchip datasheet specifies in the opcode explanations that (eg) ADDWF f,d "Add the contents of the W register with register 'F'. If d is 0, the result is stored in W. If d is 1, the result is stored back in F." It appears that CCS are trying to put 0xF into that 'd' field, so I guess the other 3 'ones' are truncated. This seems a bit of a silly thing to do! Any particular reason for it?

Thanks for any replies,
Neil.
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Original Post ID: 10050

[Tomi]

The second parameter is the target of the operation. It could be either "W" (W register, coded as 0 in machine code) or "F" (File Register, coded as 1 in machine code).
It is more readable and comfortable to use:
ANDWF 0x0F,F or
ANDWF 0x0F,W rather than:
ANDWF 0x0F,1 or
ANDWF 0x0F,0

So the "F" at the 2nd oper. is the mnemonic of "File Register" and not hexa "F".
Note that you can use the "F" mnemonic in assembler, e.g.:
#asm
andwf 0x0f,f
#endasm
gives the right result.


:=I'm sure there will be a valid reason, but can anyone explain why the ASM generated by CCS uses 'F' instead of 0 or 1 for the second field for some opcodes? The Microchip datasheet specifies in the opcode explanations that (eg) ADDWF f,d "Add the contents of the W register with register 'F'. If d is 0, the result is stored in W. If d is 1, the result is stored back in F." It appears that CCS are trying to put 0xF into that 'd' field, so I guess the other 3 'ones' are truncated. This seems a bit of a silly thing to do! Any particular reason for it?
:=
:=Thanks for any replies,
:=Neil.
___________________________
This message was ported from CCS's old forum
Original Post ID: 10051

[neil]

Duh, Silly me! Thanks for setting that one straight!
___________________________
This message was ported from CCS's old forum
Original Post ID: 10052