CCS C Software and Maintenance Offers
FAQFAQ   FAQForum Help   FAQOfficial CCS Support   SearchSearch  RegisterRegister 

ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

CCS does not monitor this forum on a regular basis.

Please do not post bug reports on this forum. Send them to CCS Technical Support

More than one Interrupts

 
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion
View previous topic :: View next topic  
Author Message
prayami



Joined: 22 Dec 2004
Posts: 78

View user's profile Send private message

More than one Interrupts
PostPosted: Wed Dec 22, 2004 7:55 pm     Reply with quote

Hi..

We are using 18F4525 and PCH Compiler.
I got all ready three interrupt and will be more two interrupts.

What happen if ISR of one interrupt is serving and at the same time
Timer0 overflows means RTCC interrupt generates?

Will RTCC interrupt will be served after servising the current interrupt?

I really got problem in generating the output frequency.
Can anybody give idea, How can I handle of the interrupt properly
without missing any of them?

If you can give example of any two interrupt then will be helpful to
write for all other interrupts.

Thank u....
dyeatman



Joined: 06 Sep 2003
Posts: 1934
Location: Norman, OK

View user's profile Send private message

Interrupts
PostPosted: Wed Dec 22, 2004 8:41 pm     Reply with quote

Since we dont know how you are doing the interrupts at this point, basically the priority keyword sets the order in which interrupts are serviced. Regular interrupts cannot interrupt each other however, on the 18F a high priority interrupt can. Ttelmah does a good job of explaining it here:

http://www.ccsinfo.com/forum/viewtopic.php?t=21213
prayami



Joined: 22 Dec 2004
Posts: 78

View user's profile Send private message

PostPosted: Wed Dec 22, 2004 9:07 pm     Reply with quote

Hi...

if Regular interrupts cannot interrupt each other.
Can we check the status of the other Interrupt flag at the end
of the current ISR and service the other function over there?

Quote:

#int_ccp2
void ccp2_isr()
{
----------

Timer0 overflaws here.....

Can we check the Timer0IF flag at the end of this ISR?
or flag will not be set at all?

I don't mind priorities. I will have five such interrupts.
How can "fast" keyword be helpful?

}


I won't mind the sequence but I want all ISR must served if
interrupt occurs....

I don't know, what exactly happen to the Interrupt flags while
interrupt is generated while other ISR is executing.
Is it something like....
While one ISR is executing and Timer0 overflaws and Timer0IF is
set. And when the current ISR is finished then all flags including
Timer0IF made to 0.

or

No flags are being set while one ISR is running even though Timer0
overflaws or what ever?

If I give Priority, then is it possible the interrupts executed one after
another in the specified sequence if some interrupt occurs while
other interrupt's ISR is running...I think not....

Wright now I got three interrupts, Can I use "fast" keyword to more
than one ISR and will the all ISR served one after another if one "fast"
interrupt is generated while other "fast" ISR is running?


Thank u...
Display posts from previous:   
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion All times are GMT - 6 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Powered by phpBB © 2001, 2005 phpBB Group