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ChrisS
Joined: 29 Nov 2004
Posts: 4
Location: PA
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 Posted: Mon Nov 29, 2004 4:06 pm |
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| Question then....does it need to be a buffered register that the data comes into? if you are loading the comparator at the same instant its comparing to the counter could it produce a glitch in the comparator output? Next...for Dave's sake, if you want to consider doing it this way, the cpld chips are pretty cheap i think...the way I went was with the free Xilinx webpack like you mentioned. There is a little programming dongle that costs $95 that you use program the chip from the webpack software on your PC . Also, the webpack software allows you to create your logic a few different ways. One way is by writing code in VHDL or Verilog, but there is also a whole graphical interface that allows you to actually create your logic graphically, just like you would a schematic of logic gates, etc. you literally pick and place little logic symbols on your screen and connect them with lines like your drawing a schematic. Then you download it to the chip. Its actually very cool and extremely easy. I guess doing that way is a little like programming in Visual Basic as opposed to assembler...its quick and easy but not necessarily the most resourceful or streamlined way...that is what I have heard, but for my apps. it has worked great. Maybe someone else has more input on this. You can find all the info you need and chips and parts on Xilinx.com |
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John P
Joined: 17 Sep 2003
Posts: 331
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| Posted: Mon Nov 29, 2004 8:03 pm |
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I've done an 8-channel PWM on a PIC16F877, running at 60hz. Wouldn't you want to use 60Hz, if these lamps run off the power line? Mine had a resolution of 1%, but it could have been more.
250KHz is a brisk data rate, but I think it's workable. My approach is usually to set up a timer running as fast as needed to catch every incoming character by polling, interrupting only on the timer. The characters just get stuffed into a buffer, for processing outside the interrupt. Then the other thing the timer does is get divided down to whatever you need to run the outputs, and calculate whether a given output needs to change or not. Since there are 8 outputs, you could have a register associated with each one, which would be its turn-off time, or 0 if it never turned on. So every timer tick, you'd check the 8 registers to see whether any changes were needed in the outputs. At tick 0, you'd turn on every output whose register held a non-zero value. |
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Guest
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| Posted: Tue Nov 30, 2004 1:59 am |
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John, sorry, I have drifted off the original posting a little, but it was a question of producing 24 pwm channels at about 2Khz i think...dont think he is intending on using it for a dimmer, but he didnt say...I was just relating it to a pwm application I did once that was for AC dimmers and recieved DMX like he also wants to do. I'm sure that with a 40Mhz PIC and enough tweeking of code he could make 8 channels work. I was trying to think of some other options that would give him more headroom. He needs 24 channels of PWM, so he will obviousely need a multi-chip solution I think.
I have never tried receiving asyncronous data by polling the receiver. It would seem like you would have to pole at several times the frame rate of the data coming in in order to guarantee you'll catch each byte. I guess that might work up to a certain number of PWM channels. If you want 8 bit resolution, your clock ticks have to be at a frequency 256 times as fast as your duty cycle right? and you have to update all your registers within the time of each of those ticks.
One thing that DMX does have going for it in his favor is that each channel value is sent only once per packet, and there is usually a small amount of idle time (maybe a few milliseconds) before the next packet comes along. I have used this time before to do any data processing I have, so that on top of the timing-critical pulse shaping thats going on, I'm only doing one other thing at any given time...either receiving data, or processing it. It all comes down to a question of do you have enough bandwidth around your PWM routines to take care of everything else in a timely fashion. Anyway, if you read the first few posts your get an idea of what he needs. |
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davt
Joined: 07 Oct 2003
Posts: 66
Location: England
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| Posted: Tue Nov 30, 2004 4:01 am |
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Thanks everybody for your input!
Mark you must be a very clever fellow or have very long lunch breaks - obviously the former! 
I am dimming Led's so am using PWM - or maybe someone can advise an alternative?
I have built an analogue lighting board of 20 channels using 10x12f675 (2 software PWM's / chip) I thought it would be nice to go digital (DMX)throughout and try and put it all onto one chip.
I suppose I could go down to 400 or 500 hundred Hz or maybe lower so long as I can avoide flicker.
Regards.
Dave |
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Mark
Joined: 07 Sep 2003
Posts: 2838
Location: Atlanta, GA
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| Posted: Tue Nov 30, 2004 7:20 am |
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| One Hundred Hertz is the typical "no visible flicker" frequency. I am more inclined to believe that 100Hz-500Hz is doable in a single PIC. Are you limited to just the 16 series or do you have the PCH compiler for the 18's |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Tue Nov 30, 2004 9:17 am |
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| Quote: | | I am dimming Led's so am using PWM - or maybe someone can advise an alternative? |
I wondered if that was your application.
Look at the TLC59xx series of LED drivers, such as the TLC5904.
They will do 256 gray levels (or more). For a small number of LEDs,
they're a better solution than the FPGA mentioned previously, because
they have built-in constant current drivers and other features. With an
FPGA, you would have to add an external constant current driver chip.
In the US, they are available from http://www.digikey.com
http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?templateId=5¶mTable=yes&familyId=480 |
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davt
Joined: 07 Oct 2003
Posts: 66
Location: England
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| Posted: Tue Nov 30, 2004 9:37 am |
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Mark
I have PCW 3.21 so I should be OK.
Can you give me a bit more detailed explanation of how to set up for the multiple PWM's.
Thank you 'pcm programmer' I will look into those chips!!
Many thanks Mark.
Dave |
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Mark
Joined: 07 Sep 2003
Posts: 2838
Location: Atlanta, GA
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| Posted: Tue Nov 30, 2004 6:31 pm |
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| Did a little testing today and at 20MHz a PIC18 was a bit stressed with the default int handler. I test it with a custom one tomorrow and see how it goes. I'll post you some code to go along with it. |
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davt
Joined: 07 Oct 2003
Posts: 66
Location: England
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| Posted: Thu Dec 02, 2004 3:34 am |
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Thanks for that Mark  |
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Mark
Joined: 07 Sep 2003
Posts: 2838
Location: Atlanta, GA
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| Posted: Thu Dec 02, 2004 8:25 am |
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Okay, here is a program that will receive the first 24 channels of a DMX stream and generate 24 8bit 200Hz PWM's. You could probably up it just a bit more with the present 20MHz clock or a lot more if you run it at 40MHz (which is what I would do but didn't have a board with that value for testing). I tried to comment best I could and refrained from using assmebler for the most part 
The C file
| Code: |
#CASE
#include "18F252_.h"
/* used to setup device specifications for programming the chips
HS - oscillator type
WDT- watchdog timer
NOPROTECT - do not protect code
PUT - power up timer on
BROWNOUT - brownout detect on */
#fuses NOLVP, HS, NOWDT, PUT, BROWNOUT, NOPROTECT
/* initialize all RAM locations to zero */
#ZERO_RAM
#define CLOCK_FREQUENCY 20000000
#define FOSC (CLOCK_FREQUENCY/4)
#USE DELAY(CLOCK = CLOCK_FREQUENCY)
#USE STANDARD_IO(A)
#USE STANDARD_IO(B)
#USE STANDARD_IO(C)
/* DMX is 250K baud. I wouldn't put errors in here. It is handled
in the int. */
#USE RS232(baud=250000,rcv=PIN_C7,xmit=PIN_C6)
/* Timer1 prescale value */
#define T1_PRESCALE 1
/* This is the frequency of the PWM. To find out the max frequency,
you should sum the max time of the CCP2 isr and the DMX recv int
Now multiply that by 256 and that will give you the period. */
#define PWM_FQ 200
/* This sets the size of our buffers. */
#define MAX_PWMS 24
#define MAX_PWM_ARRAY (((MAX_PWMS-1)/8)+1)
/* This would be the width of the smallest pulse, level = 1 */
#define PWM_STEP (((FOSC/256)/T1_PRESCALE)/PWM_FQ)
/* This is the period for the PWM. I substracted 1 from the
value so that a level of 255 would actually exceed the period
of the PWM and thus the outputs would never turn off */
const int16 PWM_PERIOD = (255*PWM_STEP)-1;
/****************************************************************************
* Card IO *
****************************************************************************/
/* This was the IO for a card I did some testing with. You will need to
setup the IO per your hardware. */
/*
The IO on this card is as follows:
RA0 - RA5 - Used to test the PWMs
TRISA - 0000 0000 - 00h
RB0 - INT - Zero Cross Interrupt (input)
RB1 - LED - I2C Bus Indication (output)
RB2 - LED - developers choice (output)
RB3 - not used (input)
RB4 - CTS input for RS-232 (not used unless LT1180A chip is there)
RB5 - RTS output for RS-232 (not used unless LT1180A chip is there)
RB6 - PGC - in circuit programming (input)
RB7 - PGD - in circuit programming (input)
TRISB - 1101 1001 - D9h
RC0 - QH of 74165 shift register (input)
RC1 - SHIFTREG_CKL of 74165 shift register (output)
RC2 - SHIFTREG_LOAD of 74165 shift register (output)
RC3 - SCL for I2C bus (input)
RC4 - SDA for I2C bus (input)
RC5 - RS-485 TXEN (or RS232) (output)
RC6 - RS-485 TXD (or RS232) (output)
RC7 - RS-485 RXD (or RS232) (input)
TRISC - 1001 1001 - 99h
TRIS masks are:
0 = OUTPUT
1 = INPUT
*/
#define PORT_A_TRIS_MASK 0x00
#define PORT_B_TRIS_MASK 0xD9
#define PORT_C_TRIS_MASK 0x99
#define RS485_TRANSMIT_DISABLE() PORTCbits.RC5=0
#define RS485_TRANSMIT_ENABLE() PORTCbits.RC5=1
/****************************************************************************
* ISR Save Variables *
****************************************************************************/
int16 fsr0_save;
#locate fsr0_save = 0x05
int8 W_save;
#locate W_save = 0x07
int8 STATUS_save;
#locate STATUS_save = 0x08
int8 BSR_save;
#locate BSR_save = 0x09
int8 SCRATCH3_save;
#locate SCRATCH3_save = 0x0A
typedef struct
{
int16 pwm_value;
int8 outputs[MAX_PWM_ARRAY];
}PWM_LIST_TYPE;
typedef struct
{
int8 level;
int8 channel;
}LEVEL_LIST_TYPE;
/* Rx buffer for DMX stream */
int8 Rx_Buffer[MAX_PWMS];
/* current levels - 0 to 255 */
int8 DMX_Levels[MAX_PWMS];
/* We have 2 ccp value arrays for doubling buffering to
prevent any glitches */
PWM_LIST_TYPE PWM_List1[MAX_PWMS+1];
PWM_LIST_TYPE PWM_List2[MAX_PWMS+1];
/* Pointer to our ccp data that the isr is using */
volatile PWM_LIST_TYPE *ptrPWM_List;
int1 Check_Levels=0;
int1 Use_PWM_List1=1;
int1 ISR_using_PWM_List1=1;
/****************************************************************************
* DESCRIPTION: Function for comparing 2 items in an array
* RETURN: (-1) if item1 < item2
* ( 0) if item1 = item2
* (+1) if item1 > item2
* ALGORITHM: none
* NOTES: none
****************************************************************************
*/
signed int8 compare(
LEVEL_LIST_TYPE *arg1, // Item 1 from the array
LEVEL_LIST_TYPE *arg2) // Item 2 from the array
{
if (arg1->level < arg2->level)
return (-1);
else if (arg1->level == arg2->level)
return (0);
else
return (1);
}
/****************************************************************************
* DESCRIPTION: Modified insertion sort for sorting our levels in ascending
* order
* RETURN: none
* ALGORITHM: none
* NOTES: none
****************************************************************************
*/
void isort(
LEVEL_LIST_TYPE *base, // point to the list to sort
int8 nmemb, // number of elements in list
int8 size) // size of each element
{
LEVEL_LIST_TYPE *i, *j, *lim;
/* pointer past end of array */
lim = &base[nmemb];
for (j = base, i = j; i < lim; j = i, i++)
{
for (; compare(j, (j + 1)) > 0; j--)
{
char *a, *b;
char tmp;
int8 k;
k = sizeof(base[0]);
a = (char*)j;
b = a + sizeof(base[0]);
do
{
tmp = *a;
*a++ = *b;
*b++ = tmp;
} while (--k);
if (j == base)
break;
}
}
}
/* *************************************************************************
DESCRIPTION: This function clears a bit in an array of byte(s).
RETURN: none
ALGORITHM: none
NOTES: none
****************************************************************************/
void clear_bit(
int8 *p, // pointer to the array of bits
int8 b) // which bit to clear
{
int8 index;
index = b / 8;
b &= 0b00000111;
*(p + index) &= ~(1<<b);
}
/* *************************************************************************
DESCRIPTION: This function computes the ccp values for our DMX levels
RETURN: none
ALGORITHM: none
NOTES: none
****************************************************************************/
void compute_pwm_values(PWM_LIST_TYPE *PWM_List)
{
int8 i, j, level, outputs[MAX_PWM_ARRAY];
LEVEL_LIST_TYPE level_list[MAX_PWMS];
PWM_LIST_TYPE *ptrList;
/* build a list of DMX level along with their index.
We will sort the list so the */
for (i=0;i<MAX_PWMS;i++)
{
level_list[i].level = DMX_Levels[i];
level_list[i].channel = i;
}
/* now sort that list */
isort(level_list,MAX_PWMS,sizeof(level_list[0]));
/* Start with all the outputs on */
memset(outputs,0xFF,MAX_PWM_ARRAY);
/* find all the outputs that are off. This will be our starting mask */
i = 0;
while ((level_list[i].level == 0) && (i < MAX_PWMS))
{
clear_bit(outputs, level_list[i].channel);
i++;
}
/* These are the initial levels of the outputs */
for (j=0;j<MAX_PWM_ARRAY;j++)
PWM_List[0].outputs[j] = outputs[j];
PWM_List[0].pwm_value = 0xFFFF;
/* Load all the ccp values into an array */
level = 0;
ptrList=PWM_List;
for (;i<MAX_PWMS;i++)
{
/* we are only loading unique values */
if (level_list[i].level != level)
{
level = level_list[i].level;
/* this is where we actually compute the ccp value.
Note that this is a short cut for doing the math.
Also, don't use an array here because the compiler
will do a little multiplying itself and destory the
value we just computed. */
W = level;
#asm
mullw PWM_STEP
#endasm
ptrList->pwm_value = PROD;
ptrList++;
}
/* test if these outputs are always on. If so then we are done */
if (level_list[i].level == 0xFF)
break;
/* Time for this output to turn off */
clear_bit(outputs, level_list[i].channel);
/* Store the output mask. Note that we always set the ccp
value to the max to prevent the ccp2 int from firing once
we are done. The outputs are set at the same time the next
ccp value is set. Therefore, if this were the last output
then we would not want the ccp to fire again. */
ptrList->pwm_value = 0xFFFF;
for (j=0;j<MAX_PWM_ARRAY;j++)
ptrList->outputs[j] = outputs[j];
}
}
/****************************************************************************
* DESCRIPTION: This is the "main" function. It performs the proper
* initialization, then starts the main loop of the program.
* RETURN: none
* ALGORITHM: none
* NOTES: none
*****************************************************************************/
void main(void)
{
int8 i;
int1 time_to_update=0;
/* Setup our IO */
setup_adc_ports( NO_ANALOGS );
set_tris_a(PORT_A_TRIS_MASK);
set_tris_b(PORT_B_TRIS_MASK);
set_tris_c(PORT_C_TRIS_MASK);
/* We only receive DMX */
RS485_TRANSMIT_DISABLE();
/* Enable the high priority interrupts */
IPR1 = 0x04; // CCP1 high priority
IPR2 = 0x01; // CCP2 high priority
INTCON3 = 0;
INTCON2 = 0xF0;
RCONbits.IPEN = 1;
/* Initialize the Rx_Buffer and DMX_Levels to off */
memset(DMX_Levels,0,MAX_PWMS);
memset(Rx_Buffer,0,MAX_PWMS);
/* Compute the initial pwm_values */
compute_pwm_values(PWM_List1);
/* Tell the ISR to use PWM_List1 for its data points */
Use_PWM_List1 = 1;
/* setup our period for our PWM */
CCPR1 = PWM_PERIOD;
/* We are going to use 2 ccp modules. CCP1 for our period
and CCP2 to control the pulse width */
setup_ccp1(CCP_COMPARE_RESET_TIMER);
setup_ccp2(CCP_COMPARE_INT);
/* Don't worry about enabling CCP2 just yet, the CCP1 int will
take care of that */
enable_interrupts(INT_CCP1);
/* Setup timer1 */
set_timer1(0);
setup_timer_1(T1_INTERNAL | T1_DIV_BY_1);
enable_interrupts(INT_RDA);
enable_interrupts(GLOBAL);
while (1)
{
/* After each data packet, the receive int will set this flag
to allow us to check for a change. Not the most efficient means
but it works. We could check for a difference in the int and set
a flag if we need more horsepower in the main loop at a sacrifice
of a few more instructions in the receive int */
if (Check_Levels)
{
Check_Levels = 0;
for (i=0;i<MAX_PWMS;i++)
{
if (DMX_Levels[i] != Rx_Buffer[i])
{
DMX_Levels[i] = Rx_Buffer[i];
time_to_update = 1;
}
}
/* Some levels had changed so we need to get new ccp values */
if (time_to_update)
{
time_to_update = 0;
/* Now we really can't change the ccp values that the int
is using so we have another set to load while the int
is using the first set. */
if (Use_PWM_List1)
{
/* Here we are waiting until the ISR gets the right pointer.
we might have told the isr to use it but it was still using
the last set so we need to wait until the isr sets its pointer */
while(!ISR_using_PWM_List1);
compute_pwm_values(PWM_List2);
Use_PWM_List1 = 0;
}
else
{
/* Wait until the ISR gets the right pointer */
while(ISR_using_PWM_List1);
compute_pwm_values(PWM_List1);
Use_PWM_List1 = 1;
}
}
}
} /* end of forever loop */
}
/****************************************************************************
* ISR routines *
****************************************************************************/
/****************************************************************************
* DESCRIPTION: CCP2 int is responsible for turning off outputs and loading
* the next turn off point. This is the pulse width control.
* RETURN: none
* ALGORITHM: none
* NOTES: none
*****************************************************************************/
void ccp2_isr(void)
{
/* Get the next set of values */
ptrPWM_List++;
/* Load the next turnoff point */
CCPR2 = ptrPWM_List->pwm_value;
/* set the current state of the outputs */
PORTA = ptrPWM_List->outputs[0];
// PORTB = ptrPWM_List->outputs[1];
// PORTD = ptrPWM_List->outputs[2];
/* Clear the interrupt flag only if our CCP value will
still occur. If it is in the past then go ahead
and let the int occur back to back. This probably
isn't necessary but a little assurance can't hurt. */
if (CCPR2>TMR1)
clear_interrupt(INT_CCP2);
}
/****************************************************************************
* DESCRIPTION: This int controls the period of our PWM's and loads the
* initial turn off point for the pwm's
* RETURN: none
* ALGORITHM: none
* NOTES: none
*****************************************************************************/
void ccp1_isr(void)
{
clear_interrupt(INT_CCP1);
/* Reset our pointer. We have two sets of values
since we are always using one set. This double
buffering gives us glitch less operation */
if (Use_PWM_List1)
{
ptrPWM_List = PWM_List1;
/* Notify the main loop that we are indeed using the
PWM_List1 values. */
ISR_using_PWM_List1=1;
}
else
{
ptrPWM_List = PWM_List2;
/* Notify the main loop that we are not using the
PWM_List1 values. */
ISR_using_PWM_List1=0;
}
/* set the inital state of the outputs */
PORTA = ptrPWM_List->outputs[0];
// PORTB = ptrPWM_List->outputs[1];
// PORTD = ptrPWM_List->outputs[2];
/* load the inital ccp value and enable the int */
CCPR2 = ptrPWM_List->pwm_value;
/* Clear the interrupt flag only if our CCP value will
still occur. If it is in the past then go ahead
and let the int occur back to back. This probably
isn't necessary but a little assurance can't hurt. */
if (CCPR2<TMR1)
PIR2bits.CCP2IF = 1;
else
clear_interrupt(INT_CCP2);
enable_interrupts(INT_CCP2);
}
/****************************************************************************
* DESCRIPTION: Receives DMX data stream
* RETURN: none
* ALGORITHM: none
* NOTES: none
*****************************************************************************/
void dmx_rcv(void)
{
/* Our different receive states */
#define WAIT_FOR_NEXT_BYTE 0
#define WAIT_FOR_BREAK 1
#define WAIT_FOR_START 2
#define RECEIVE_DATA 3
/* State machine for determining the begining of the DMX stream */
static int8 Rx_State = WAIT_FOR_BREAK;
/* Data that we are receiving */
int8 data;
/* Duplicate of the RCSTA reg used due to the double buffering of the
fifo. Reading the RCREG reg will cause the second RCSTA reg to be
loaded if there is one. */
union
{
unsigned char byte;
struct {
unsigned char RX9D:1;
unsigned char OERR:1;
unsigned char FERR:1;
unsigned char ADDEN:1;
unsigned char CREN:1;
unsigned char SREN:1;
unsigned char RX9:1;
unsigned char SPEN:1;
} bits ;
}rcsta;
/* receive buffer index */
static int8 *ptr_Rx;
while (PIR1bits.RCIF)
{
/* Read the data and the Rx status reg */
rcsta.byte = RCSTA;
data = RCREG;
/* Check for buffer overrun error */
if (RCSTAbits.OERR)
{
RCSTAbits.CREN=0;
RCSTAbits.CREN=1;
/* we just received a buffer overrun so lets wait
for a good data byte before we look for the break signal. */
Rx_State = WAIT_FOR_NEXT_BYTE;
return;
}
switch (Rx_State)
{
case WAIT_FOR_NEXT_BYTE:
if (!rcsta.bits.FERR)
Rx_State = WAIT_FOR_BREAK;
break;
case WAIT_FOR_BREAK:
/* Check for a framing error */
if (rcsta.bits.FERR)
{
/* If we did receive a framing error, make sure that the data is 0.
This means that we did Rx the break signal for at least 44us. */
if (!data)
Rx_State = WAIT_FOR_START;
}
break;
case WAIT_FOR_START:
/* Check for a framing error. If we receive one then we need to wait
until we receive a good data byte before we begin looking for our
Break signal */
if (rcsta.bits.FERR)
Rx_State = WAIT_FOR_NEXT_BYTE;
/* The start code for our data packet should always start with 0. */
else
{
if (!data)
{
/* Initialize our pointer to our Rx buffer. */
ptr_Rx = Rx_Buffer;
Rx_State = RECEIVE_DATA;
}
else
Rx_State = WAIT_FOR_BREAK;
}
break;
case RECEIVE_DATA:
/* check for framing error - if we receive a framing error then this
might be the begining of the next packet or a true framing error. */
if (rcsta.bits.FERR)
{
/* if this is the beginging of the next frame then data must = 0
else this is a framing error. */
if (!data)
Rx_State = WAIT_FOR_START;
else
Rx_State = WAIT_FOR_NEXT_BYTE;
}
else
{
/* Store the data received in the Rx buffer */
*ptr_Rx = data;
/* Point to the next byte */
ptr_Rx++;
/* Check to see if we have received all of our data */
if (ptr_Rx > &Rx_Buffer[MAX_PWMS-1])
{
/* we received all the data so see if anything has changed */
Check_Levels = 1;
Rx_State = WAIT_FOR_BREAK;
}
}
break;
}
}
return;
}
/****************************************************************************
* DESCRIPTION: The int handler for high priority interrupts
* PARAMETERS: none
* RETURN: none
* ALGORITHM: none
* NOTES: none
*****************************************************************************/
void Int_Handler_High(void)
{
/* Currently these ints only use FSR0 and register 3
so that is all that we need to save */
fsr0_save = FSR0;
SCRATCH3_save = *(0x03);
/* Check for a CCP2 interrupt */
if ((PIE2bits.CCP2IE) && (PIR2bits.CCP2IF))
ccp2_isr();
/* Check for a CCP1 interrupt */
if ((PIE1bits.CCP1IE) && (PIR1bits.CCP1IF))
ccp1_isr();
/* restore data */
FSR0 = fsr0_save;
*(0x03) = SCRATCH3_save;
#asm
retfie 1
#endasm
}
#org 0x08,0x0A
/****************************************************************************
* DESCRIPTION: Wrapper for the high priority interrupt
* RETURN: none
* ALGORITHM: none
* NOTES: none
*****************************************************************************/
void Int_Handler_High_Wrapper(void)
{
Int_Handler_High();
}
/****************************************************************************
* DESCRIPTION: The int handler for low priority interrupts
* RETURN: none
* ALGORITHM: none
* NOTES: none
*****************************************************************************/
#org 0x18,0x48
void Int_Handler_Low(void)
{
#asm
movwf W_save
#endasm
STATUS_save = STATUS;
fsr0_save = FSR0;
BSR_save = BSR;
if ((PIR1bits.RCIF) && (PIE1bits.RCIE))
dmx_rcv();
BSR = BSR_save;
FSR0 = fsr0_save;
#asm
movf W_save,W
#endasm
STATUS = STATUS_save;
#asm
retfie 0
#endasm
}
|
The 18F252_.h file
| Code: |
#ifndef 18F252_H
#define 18F252_H
#device PIC18F252 *=16
/**************************** Standard Header file for the PIC18F252 device
Program memory: 16384x16 Data RAM: 1536 Stack: 31
I/O: 22 Analog Pins: 5
Data EEPROM: 256
C Scratch area: 00 ID Location: 2000
Fuses: LP,XT,HS,RC,EC,EC_IO,H4,RC_IO,PROTECT,NOPROTECT,OSCSEN
Fuses: NOOSCSEN,NOBROWNOUT,BROWNOUT,WDT1,WDT2,WDT4,WDT8,WDT16,WDT32
Fuses: WDT64,WDT128,WDT,NOWDT,BORV20,BORV27,BORV42,BORV45,PUT,NOPUT
Fuses: CCP2C1,CCP2B3,NOSTVREN,STVREN,NODEBUG,DEBUG,NOLVP,LVP,WRT
Fuses: NOWRT,WRTD,NOWRTD,WRTB,NOWRTB
***************************************************************************/
/********************************************************************** I/O
Discrete I/O Functions: SET_TRIS_x(), OUTPUT_x(), INPUT_x(),
PORT_B_PULLUPS(), INPUT(),
OUTPUT_LOW(), OUTPUT_HIGH(),
OUTPUT_FLOAT(), OUTPUT_BIT()
Constants used to identify pins in the above are:
***************************************************************************/
#define PIN_A0 31744
#define PIN_A1 31745
#define PIN_A2 31746
#define PIN_A3 31747
#define PIN_A4 31748
#define PIN_A5 31749
#define PIN_B0 31752
#define PIN_B1 31753
#define PIN_B2 31754
#define PIN_B3 31755
#define PIN_B4 31756
#define PIN_B5 31757
#define PIN_B6 31758
#define PIN_B7 31759
#define PIN_C0 31760
#define PIN_C1 31761
#define PIN_C2 31762
#define PIN_C3 31763
#define PIN_C4 31764
#define PIN_C5 31765
#define PIN_C6 31766
#define PIN_C7 31767
/********************************************************** Useful defines
Function Registers
***************************************************************************/
unsigned char ADCON0;
#locate ADCON0=0x0FC2
union {
struct {
unsigned char ADON:1;
unsigned char UNUSED0:1;
unsigned char GO:1;
unsigned char CHS0:1;
unsigned char CHS1:1;
unsigned char CHS2:1;
unsigned char ADCS0:1;
unsigned char ADCS1:1;
} ;
struct {
unsigned char UNUSED1:2;
unsigned char NOT_DONE:1;
} ;
struct {
unsigned char UNUSED2:2;
unsigned char DONE:1;
} ;
struct {
unsigned char UNUSED3:2;
unsigned char GO_DONE:1;
} ;
} ADCON0bits ;
#locate ADCON0bits=0x0FC2
unsigned char ADCON1;
#locate ADCON1=0x0FC1
struct {
unsigned char PCFG0:1;
unsigned char PCFG1:1;
unsigned char PCFG2:1;
unsigned char PCFG3:1;
unsigned char UNUSED:2;
unsigned char ADCS2:1;
unsigned char ADFM:1;
} ADCON1bits ;
#locate ADCON1bits=0x0FC1
unsigned int16 ADRES;
#locate ADRES=0x0FC3
unsigned char ADRESH;
#locate ADRESH=0x0FC4
unsigned char ADRESL;
#locate ADRESL=0x0FC3
unsigned char BSR;
#locate BSR=0x0FE0
unsigned char CCP1CON;
#locate CCP1CON=0x0FBD
union {
struct {
unsigned char CCP1M0:1;
unsigned char CCP1M1:1;
unsigned char CCP1M2:1;
unsigned char CCP1M3:1;
unsigned char CCP1Y:1;
unsigned char CCP1X:1;
} ;
struct {
unsigned char UNUSED:4;
unsigned char DC1B0:1;
unsigned char DC1B1:1;
} ;
} CCP1CONbits ;
#locate CCP1CONbits=0x0FBD
unsigned char CCP2CON;
#locate CCP2CON=0x0FBA
union {
struct {
unsigned char CCP2M0:1;
unsigned char CCP2M1:1;
unsigned char CCP2M2:1;
unsigned char CCP2M3:1;
unsigned char CCP2Y:1;
unsigned char CCP2X:1;
} ;
struct {
unsigned char UNUSED0:4;
unsigned char DC2B0:1;
unsigned char DC2B1:1;
} ;
struct {
unsigned char UNUSED1:5;
unsigned char DCCPX:1;
} ;
} CCP2CONbits ;
#locate CCP2CONbits=0x0FBA
unsigned int16 CCPR1;
#locate CCPR1=0x0FBE
unsigned char CCPR1H;
#locate CCPR1H=0x0FBF
unsigned char CCPR1L;
#locate CCPR1L=0x0FBE
unsigned int16 CCPR2;
#locate CCPR2=0x0FBB
unsigned char CCPR2H;
#locate CCPR2H=0x0FBC
unsigned char CCPR2L;
#locate CCPR2L=0x0FBB
unsigned char DDRA;
#locate DDRA=0x0F92
struct {
unsigned char RA0:1;
unsigned char RA1:1;
unsigned char RA2:1;
unsigned char RA3:1;
unsigned char RA4:1;
unsigned char RA5:1;
unsigned char RA6:1;
unsigned char RA7:1;
} DDRAbits ;
#locate DDRAbits=0x0F92
unsigned char DDRB;
#locate DDRB=0x0F93
struct {
unsigned char RB0:1;
unsigned char RB1:1;
unsigned char RB2:1;
unsigned char RB3:1;
unsigned char RB4:1;
unsigned char RB5:1;
unsigned char RB6:1;
unsigned char RB7:1;
} DDRBbits ;
#locate DDRBbits=0x0F93
unsigned char DDRC;
#locate DDRC=0x0F94
struct {
unsigned char RC0:1;
unsigned char RC1:1;
unsigned char RC2:1;
unsigned char RC3:1;
unsigned char RC4:1;
unsigned char RC5:1;
unsigned char RC6:1;
unsigned char RC7:1;
} DDRCbits ;
#locate DDRCbits=0x0F94
unsigned char DDRD;
#locate DDRD=0x0F95
struct {
unsigned char RD0:1;
unsigned char RD1:1;
unsigned char RD2:1;
unsigned char RD3:1;
unsigned char RD4:1;
unsigned char RD5:1;
unsigned char RD6:1;
unsigned char RD7:1;
} DDRDbits ;
#locate DDRDbits=0x0F95
unsigned char DDRE;
#locate DDRE=0x0F96
struct {
unsigned char RE0:1;
unsigned char RE1:1;
unsigned char RE2:1;
unsigned char RE3:1;
unsigned char RE4:1;
unsigned char RE5:1;
unsigned char RE6:1;
unsigned char RE7:1;
} DDREbits ;
#locate DDREbits=0x0F96
unsigned char DDRF;
#locate DDRF=0x0F97
struct {
unsigned char RF0:1;
unsigned char RF1:1;
unsigned char RF2:1;
unsigned char RF3:1;
unsigned char RF4:1;
unsigned char RF5:1;
unsigned char RF6:1;
unsigned char RF7:1;
} DDRFbits ;
#locate DDRFbits=0x0F97
unsigned char DDRG;
#locate DDRG=0x0F98
struct {
unsigned char RG0:1;
unsigned char RG1:1;
unsigned char RG2:1;
unsigned char RG3:1;
unsigned char RG4:1;
} DDRGbits ;
#locate DDRGbits=0x0F98
unsigned char DDRH;
#locate DDRH=0x0F99
struct {
unsigned char RH0:1;
unsigned char RH1:1;
unsigned char RH2:1;
unsigned char RH3:1;
unsigned char RH4:1;
unsigned char RH5:1;
unsigned char RH6:1;
unsigned char RH7:1;
} DDRHbits ;
#locate DDRHbits=0x0F99
unsigned char DDRJ;
#locate DDRJ=0x0F9A
struct {
unsigned char RJ0:1;
unsigned char RJ1:1;
unsigned char RJ2:1;
unsigned char RJ3:1;
unsigned char RJ4:1;
unsigned char RJ5:1;
unsigned char RJ6:1;
unsigned char RJ7:1;
} DDRJbits ;
#locate DDRJbits=0x0F9A
unsigned char EEADR;
#locate EEADR=0x0FA9
unsigned char EECON1;
#locate EECON1=0x0FA6
struct {
unsigned char RD:1;
unsigned char WR:1;
unsigned char WREN:1;
unsigned char WRERR:1;
unsigned char FREE:1;
unsigned char UNUSED:1;
unsigned char CFGS:1;
unsigned char EEPGD:1;
} EECON1bits ;
#locate EECON1bits=0x0FA6
unsigned char EECON2;
#locate EECON2=0x0FA7
unsigned char EEDATA;
#locate EEDATA=0x0FA8
unsigned int16 FSR0;
#locate FSR0=0x0FE9
unsigned char FSR0H;
#locate FSR0H=0x0FEA
unsigned char FSR0L;
#locate FSR0L=0x0FE9
unsigned int16 FSR1;
#locate FSR1=0x0FE1
unsigned char FSR1H;
#locate FSR1H=0x0FE2
unsigned char FSR1L;
#locate FSR1L=0x0FE1
unsigned int16 FSR2;
#locate FSR2=0x0FD9
unsigned char FSR2H;
#locate FSR2H=0x0FDa
unsigned char FSR2L;
#locate FSR2L=0x0FD9
unsigned char INDF0;
#locate INDF0=0x0FEF
unsigned char INDF1;
#locate INDF1=0x0FE7
unsigned char INDF2;
#locate INDF2=0x0FDF
unsigned char INTCON;
#locate INTCON=0x0FF2
struct
{
unsigned char RBIF:1;
unsigned char INT0F:1;
unsigned char T0IF:1;
unsigned char RBIE:1;
unsigned char INT0E:1;
unsigned char T0IE:1;
unsigned char PEIE:1;
unsigned char GIE:1;
} INTCONbits;
#locate INTCONbits=0x0FF2
unsigned char INTCON2;
#locate INTCON2=0x0FF1
struct
{
unsigned char RBIP:1;
unsigned char INT3P:1;
unsigned char T0IP:1;
unsigned char INTEDG3:1;
unsigned char INTEDG2:1;
unsigned char INTEDG1:1;
unsigned char INTEDG0:1;
unsigned char RBPU:1;
} INTCON2bits ;
#locate INTCON2bits=0x0FF1
unsigned char INTCON3;
#locate INTCON3=0x0FF0
struct
{
unsigned char INT1IF:1;
unsigned char INT2IF:1;
unsigned char INT3IF:1;
unsigned char INT1IE:1;
unsigned char INT2IE:1;
unsigned char INT3IE:1;
unsigned char INT1IP:1;
unsigned char INT2IP:1;
} INTCON3bits ;
#locate INTCON3bits=0x0FF0
unsigned char IPR1;
#locate IPR1=0x0F9F
struct {
unsigned char TMR1IP:1;
unsigned char TMR2IP:1;
unsigned char CCP1IP:1;
unsigned char SSPIP:1;
unsigned char TXIP:1;
unsigned char RCIP:1;
unsigned char ADIP:1;
unsigned char PSPIP:1;
} IPR1bits ;
#locate IPR1bits=0x0F9F
unsigned char IPR2;
#locate IPR2=0x0FA2
struct {
unsigned char CCP2IP:1;
unsigned char TMR3IP:1;
unsigned char LVDIP:1;
unsigned char BCLIP:1;
unsigned char EEIP:1;
} IPR2bits ;
#locate IPR2bits=0x0FA2
unsigned char LATA;
#locate LATA=0x0F89
struct {
unsigned char LATA0:1;
unsigned char LATA1:1;
unsigned char LATA2:1;
unsigned char LATA3:1;
unsigned char LATA4:1;
unsigned char LATA5:1;
} LATAbits ;
#locate LATAbits=0x0F89
unsigned char LATB;
#locate LATB=0x0F8A
struct {
unsigned char LATB0:1;
unsigned char LATB1:1;
unsigned char LATB2:1;
unsigned char LATB3:1;
unsigned char LATB4:1;
unsigned char LATB5:1;
unsigned char LATB6:1;
unsigned char LATB7:1;
} LATBbits ;
#locate LATBbits=0x0F8A
unsigned char LATC;
#locate LATC=0x0F8B
struct {
unsigned char LATC0:1;
unsigned char LATC1:1;
unsigned char LATC2:1;
unsigned char LATC3:1;
unsigned char LATC4:1;
unsigned char LATC5:1;
unsigned char LATC6:1;
unsigned char LATC7:1;
} LATCbits ;
#locate LATCbits=0x0F8B
unsigned char LATD;
#locate LATD=0x0F8C
struct {
unsigned char LATD0:1;
unsigned char LATD1:1;
unsigned char LATD2:1;
unsigned char LATD3:1;
unsigned char LATD4:1;
unsigned char LATD5:1;
unsigned char LATD6:1;
unsigned char LATD7:1;
} LATDbits ;
#locate LATDbits=0x0F8C
unsigned char LATE;
#locate LATE=0x0F8D
struct {
unsigned char LATE0:1;
unsigned char LATE1:1;
unsigned char LATE2:1;
unsigned char LATE3:1;
unsigned char LATE4:1;
unsigned char LATE5:1;
unsigned char LATE6:1;
unsigned char LATE7:1;
} LATEbits ;
#locate LATEbits=0x0F8D
unsigned char LVDCON;
#locate LVDCON=0x0FD2
struct {
unsigned char LVDL0:1;
unsigned char LVDL1:1;
unsigned char LVDL2:1;
unsigned char LVDL3:1;
unsigned char LVDEN:1;
unsigned char VRST:1;
} LVDCONbits ;
#locate LVDCONbits=0x0FD2
unsigned char OSCCON;
#locate OSCCON=0x0FD3
struct {
unsigned char SCS:1;
} OSCCONbits ;
#locate OSCCONbits=0x0FD3
unsigned char PIE1;
#locate PIE1=0x0F9D
struct {
unsigned char TMR1IE:1;
unsigned char TMR2IE:1;
unsigned char CCP1IE:1;
unsigned char SSPIE:1;
unsigned char TXIE:1;
unsigned char RCIE:1;
unsigned char ADIE:1;
unsigned char PSPIE:1;
} PIE1bits ;
#locate PIE1bits=0x0F9D
unsigned char PIE2;
#locate PIE2=0x0FA0
struct {
unsigned char CCP2IE:1;
unsigned char TMR3IE:1;
unsigned char LVDIE:1;
unsigned char BCLIE:1;
unsigned char EEIE:1;
} PIE2bits ;
#locate PIE2bits=0x0FA0
unsigned char PIR1;
#locate PIR1=0x0F9E
struct {
unsigned char TMR1IF:1;
unsigned char TMR2IF:1;
unsigned char CCP1IF:1;
unsigned char SSPIF:1;
unsigned char TXIF:1;
unsigned char RCIF:1;
unsigned char ADIF:1;
unsigned char PSPIF:1;
} PIR1bits ;
#locate PIR1bits=0x0F9E
unsigned char PIR2;
#locate PIR2=0x0FA1
struct {
unsigned char CCP2IF:1;
unsigned char TMR3IF:1;
unsigned char LVDIF:1;
unsigned char BCLIF:1;
unsigned char EEIF:1;
} PIR2bits ;
#locate PIR2bits=0x0FA1
unsigned char PORTA;
#locate PORTA=0x0F80
struct
{
unsigned char RA0:1;
unsigned char RA1:1;
unsigned char RA2:1;
unsigned char RA3:1;
unsigned char RA4:1;
unsigned char RA5:1;
unsigned char RA6:1;
} PORTAbits ;
#locate PORTAbits=0x0F80
unsigned char PORTB;
#locate PORTB=0x0F81
struct
{
unsigned char RB0:1;
unsigned char RB1:1;
unsigned char RB2:1;
unsigned char RB3:1;
unsigned char RB4:1;
unsigned char RB5:1;
unsigned char RB6:1;
unsigned char RB7:1;
} PORTBbits ;
#locate PORTBbits=0x0F81
unsigned char PORTC;
#locate PORTC=0x0F82
struct
{
unsigned char RC0:1;
unsigned char RC1:1;
unsigned char RC2:1;
unsigned char RC3:1;
unsigned char RC4:1;
unsigned char RC5:1;
unsigned char RC6:1;
unsigned char RC7:1;
} PORTCbits ;
#locate PORTCbits=0x0F82
unsigned char PR2;
#locate PR2=0x0FCB
unsigned int16 PROD;
#locate PROD=0x0FF3
unsigned char PRODH;
#locate PRODH=0x0FF4
unsigned char PRODL;
#locate PRODL=0x0FF3
unsigned char RCON;
#locate RCON=0x0FD0
struct
{
unsigned char BOR:1;
unsigned char POR:1;
unsigned char PD:1;
unsigned char TO:1;
unsigned char RI:1;
unsigned char UNUSED1:1;
unsigned char LWRT:1;
unsigned char IPEN:1;
} RCONbits ;
#locate RCONbits=0x0FD0
unsigned char RCREG;
#locate RCREG=0x0FAE
unsigned char RCSTA;
#locate RCSTA=0x0FAB
struct {
unsigned char RX9D:1;
unsigned char OERR:1;
unsigned char FERR:1;
unsigned char ADDEN:1;
unsigned char CREN:1;
unsigned char SREN:1;
unsigned char RX9:1;
unsigned char SPEN:1;
} RCSTAbits ;
#locate RCSTAbits=0x0FAB
unsigned char SPBRG;
#locate SPBRG=0x0FAF
unsigned char SSPADD;
#locate SSPADD=0x0FC8
unsigned char SSPBUF;
#locate SSPBUF=0x0FC9
unsigned char SSPCON1;
#locate SSPCON1=0x0FC6
struct {
unsigned char SSPM0:1;
unsigned char SSPM1:1;
unsigned char SSPM2:1;
unsigned char SSPM3:1;
unsigned char CKP:1;
unsigned char SSPEN:1;
unsigned char SSPOV:1;
unsigned char WCOL:1;
} SSPCON1bits ;
#locate SSPCON1bits=0x0FC6
unsigned char SSPCON2;
#locate SSPCON2=0x0FC5
struct {
unsigned char SEN:1;
unsigned char RSEN:1;
unsigned char PEN:1;
unsigned char RCEN:1;
unsigned char ACKEN:1;
unsigned char ACKDT:1;
unsigned char ACKSTAT:1;
unsigned char GCEN:1;
} SSPCON2bits ;
#locate SSPCON2bits=0x0FC5
unsigned char SSPSTAT;
#locate SSPSTAT=0x0FC7
struct {
unsigned char BF:1;
unsigned char UA:1;
unsigned char R_W:1;
unsigned char S:1;
unsigned char P:1;
unsigned char D_A:1;
unsigned char CKE:1;
unsigned char SMP:1;
} SSPSTATbits ;
#locate SSPSTATbits=0x0FC7
unsigned char STATUS;
#locate STATUS=0x0FD8
struct {
unsigned char C:1;
unsigned char DC:1;
unsigned char Z:1;
unsigned char OV:1;
unsigned char N:1;
} STATUSbits ;
#locate STATUSbits=0x0FD8
unsigned char T1CON;
#locate T1CON=0x0FCD
struct
{
unsigned char TMR1ON:1;
unsigned char TMR1CS:1;
unsigned char NOT_T1SYNC:1;
unsigned char T1OSCEN:1;
unsigned char T1CKPS0:1;
unsigned char T1CKPS1:1;
unsigned char UNUSED0:1;
unsigned char RD16:1;
} T1CONbits ;
#locate T1CONbits=0x0FCD
unsigned char T2CON;
#locate T2CON=0x0FCA
struct {
unsigned char T2CKPS0:1;
unsigned char T2CKPS1:1;
unsigned char TMR2ON:1;
unsigned char TOUTPS0:1;
unsigned char TOUTPS1:1;
unsigned char TOUTPS2:1;
unsigned char TOUTPS3:1;
} T2CONbits ;
#locate T2CONbits=0x0FCA
unsigned int16 TMR0;
#locate TMR0=0x0FD6
unsigned char TMR0H;
#locate TMR0H=0x0FD7
unsigned char TMR0L;
#locate TMR0L=0x0FD6
unsigned int16 TMR1;
#locate TMR1=0x0FCE
unsigned char TMR1H;
#locate TMR1H=0x0FCF
unsigned char TMR1L;
#locate TMR1L=0x0FCE
unsigned char TMR2;
#locate TMR2=0x0FCC
unsigned char TRISA;
#locate TRISA=0x0F92
struct {
unsigned char TRISA0:1;
unsigned char TRISA1:1;
unsigned char TRISA2:1;
unsigned char TRISA3:1;
unsigned char TRISA4:1;
unsigned char TRISA5:1;
} TRISAbits ;
#locate TRISAbits=0x0F92
unsigned char TRISB;
#locate TRISB=0x0F93
struct {
unsigned char TRISB0:1;
unsigned char TRISB1:1;
unsigned char TRISB2:1;
unsigned char TRISB3:1;
unsigned char TRISB4:1;
unsigned char TRISB5:1;
unsigned char TRISB6:1;
unsigned char TRISB7:1;
} TRISBbits ;
#locate TRISBbits=0x0F93
unsigned char TRISC;
#locate TRISC=0x0F94
struct {
unsigned char TRISC0:1;
unsigned char TRISC1:1;
unsigned char TRISC2:1;
unsigned char TRISC3:1;
unsigned char TRISC4:1;
unsigned char TRISC5:1;
unsigned char TRISC6:1;
unsigned char TRISC7:1;
} TRISCbits ;
#locate TRISCbits=0x0F94
unsigned char TRISD;
#locate TRISD=0x0F95
struct {
unsigned char TRISD0:1;
unsigned char TRISD1:1;
unsigned char TRISD2:1;
unsigned char TRISD3:1;
unsigned char TRISD4:1;
unsigned char TRISD5:1;
unsigned char TRISD6:1;
unsigned char TRISD7:1;
} TRISDbits ;
#locate TRISDbits=0x0F95
unsigned char TRISE;
#locate TRISE=0x0F96
struct {
unsigned char TRISE0:1;
unsigned char TRISE1:1;
unsigned char TRISE2:1;
unsigned char TRISE3:1;
unsigned char TRISE4:1;
unsigned char TRISE5:1;
unsigned char TRISE6:1;
unsigned char TRISE7:1;
} TRISEbits ;
#locate TRISEbits=0x0F96
unsigned char TXREG;
#locate TXREG=0x0FAD
unsigned char TXSTA;
#locate TXSTA=0x0FAC
struct {
unsigned char TX9D:1;
unsigned char TRMT:1;
unsigned char BRGH:1;
unsigned char UNUSED:1;
unsigned char SYNC:1;
unsigned char TXEN:1;
unsigned char TX9:1;
unsigned char CSRC:1;
} TXSTAbits ;
#locate TXSTAbits=0x0FAC
unsigned char W;
#locate W=0x0FE8
unsigned char WDTCON;
#locate WDTCON=0x0FD1
struct
{
unsigned char SWDTEN:1;
} WDTCONbits ;
#locate WDTCONbits=0x0FD1
unsigned char WREG;
#locate WREG=0x0FE8
#define getc getch
#define getchar getch
#define putc putchar
/***************************************************************** Control
Control Functions: RESET_CPU(), SLEEP(), RESTART_CAUSE()
Constants returned from RESTART_CAUSE() are:
***************************************************************************/
#define WDT_TIMEOUT 4
#define MCLR_FROM_SLEEP 8
#define NORMAL_POWER_UP 12
#define BROWNOUT_RESTART 14
/***************************************************************** Timer 0
Timer 0 (AKA RTCC)Functions: SETUP_COUNTERS() or SETUP_TIMER0(),
SET_TIMER0() or SET_RTCC(),
GET_TIMER0() or GET_RTCC()
Constants used for SETUP_TIMER0() are:
***************************************************************************/
#define RTCC_INTERNAL 0
#define RTCC_EXT_L_TO_H 32
#define RTCC_EXT_H_TO_L 48
#define RTCC_DIV_2 0
#define RTCC_DIV_4 1
#define RTCC_DIV_8 2
#define RTCC_DIV_16 3
#define RTCC_DIV_32 4
#define RTCC_DIV_64 5
#define RTCC_DIV_128 6
#define RTCC_DIV_256 7
#define WDT_18MS 8
#define WDT_36MS 9
#define WDT_72MS 10
#define WDT_144MS 11
#define WDT_288MS 12
#define WDT_576MS 13
#define WDT_1152MS 14
#define WDT_2304MS 15
#define RTCC_OFF 0x80
#define RTCC_8_BIT 0x40
/******************************************************
Constants used for SETUP_COUNTERS() are the above
constants for the 1st param and the following for
the 2nd param:
******************************************************/
/********************************************************************* WDT
Watch Dog Timer Functions: SETUP_WDT() or SETUP_COUNTERS() (see above)
RESTART_WDT()
***************************************************************************/
#define WDT_ON 0x100
#define WDT_OFF 0
/***************************************************************** Timer 1
Timer 1 Functions: SETUP_TIMER_1, GET_TIMER1, SET_TIMER1
Constants used for SETUP_TIMER_1() are:
(or (via |) together constants from each group)
***************************************************************************/
#define T1_DISABLED 0
#define T1_INTERNAL 0x85
#define T1_EXTERNAL 0x87
#define T1_EXTERNAL_SYNC 0x83
#define T1_CLK_OUT 8
#define T1_DIV_BY_1 0
#define T1_DIV_BY_2 0x10
#define T1_DIV_BY_4 0x20
#define T1_DIV_BY_8 0x30
#byte TIMER_1_LOW= 0xFD6
#byte TIMER_1_HIGH= 0xFD7
/***************************************************************** Timer 2
Timer 2 Functions: SETUP_TIMER_2, GET_TIMER2, SET_TIMER2
Constants used for SETUP_TIMER_2() are:
***************************************************************************/
#define T2_DISABLED 0
#define T2_DIV_BY_1 4
#define T2_DIV_BY_4 5
#define T2_DIV_BY_16 6
#byte TIMER_2= 0xFCC
/***************************************************************** Timer 3
Timer 3 Functions: SETUP_TIMER_3, GET_TIMER3, SET_TIMER3
Constants used for SETUP_TIMER_3() are:
(or (via |) together constants from each group)
***************************************************************************/
#define T3_DISABLED 0
#define T3_INTERNAL 0x85
#define T3_EXTERNAL 0x87
#define T3_EXTERNAL_SYNC 0x83
#define T3_DIV_BY_1 0
#define T3_DIV_BY_2 0x10
#define T3_DIV_BY_4 0x20
#define T3_DIV_BY_8 0x30
/********************************************************************* CCP
CCP Functions: SETUP_CCPx, SET_PWMx_DUTY
CCP Variables: CCP_x, CCP_x_LOW, CCP_x_HIGH
Constants used for SETUP_CCPx() are:
***************************************************************************/
#define CCP_OFF 0
#define CCP_CAPTURE_FE 4
#define CCP_CAPTURE_RE 5
#define CCP_CAPTURE_DIV_4 6
#define CCP_CAPTURE_DIV_16 7
#define CCP_COMPARE_SET_ON_MATCH 8
#define CCP_COMPARE_CLR_ON_MATCH 9
#define CCP_COMPARE_INT 0xA
#define CCP_COMPARE_RESET_TIMER 0xB
#define CCP_PWM 0xC
#define CCP_PWM_PLUS_1 0x1c
#define CCP_PWM_PLUS_2 0x2c
#define CCP_PWM_PLUS_3 0x3c
#define CCP_USE_TIMER3 0x100
long CCP_1;
#byte CCP_1 = 0xfbe
#byte CCP_1_LOW= 0xfbe
#byte CCP_1_HIGH= 0xfbf
long CCP_2;
#byte CCP_2 = 0xfbb
#byte CCP_2_LOW= 0xfbb
#byte CCP_2_HIGH= 0xfbc
/******************************************************************** SPI
SPI Functions: SETUP_SPI, SPI_WRITE, SPI_READ, SPI_DATA_IN
Constants used in SETUP_SSP() are:
***************************************************************************/
#define SPI_MASTER 0x20
#define SPI_SLAVE 0x24
#define SPI_L_TO_H 0
#define SPI_H_TO_L 0x10
#define SPI_CLK_DIV_4 0
#define SPI_CLK_DIV_16 1
#define SPI_CLK_DIV_64 2
#define SPI_CLK_T2 3
#define SPI_SS_DISABLED 1
#define SPI_SAMPLE_AT_END 0x8000
#define SPI_XMIT_L_TO_H 0x4000
/********************************************************************* ADC
ADC Functions: SETUP_ADC(), SETUP_ADC_PORTS() (aka SETUP_PORT_A),
SET_ADC_CHANNEL(), READ_ADC()
Constants used in SETUP_ADC_PORTS() are:
***************************************************************************/
#define NO_ANALOGS 0x06 /* None */
#define ALL_ANALOG 0x00 /* RA0 RA1 RA2 RA3 RA5 RE0 RE1 RE2 Ref=Vdd */
#define ANALOG_RA3_REF 0x01 /* RA0 RA1 RA2 RA5 RE0 RE1 RE2 Ref=RA3 */
#define A_ANALOG 0x02 /* RA0 RA1 RA2 RA3 RA5 Ref=Vdd */
#define A_ANALOG_RA3_REF 0x03 /* RA0 RA1 RA2 RA5 Ref=RA3 */
#define RA0_RA1_RA3_ANALOG 0x04 /* RA0 RA1 RA3 Ref=Vdd */
#define RA0_RA1_ANALOG_RA3_REF 0x05 /* RA0 RA1 Ref=RA3 */
#define ANALOG_RA3_RA2_REF 0x08
#define ANALOG_NOT_RE1_RE2 0x09
#define ANALOG_NOT_RE1_RE2_REF_RA3 0x0A
#define ANALOG_NOT_RE1_RE2_REF_RA3_RA2 0x0B
#define A_ANALOG_RA3_RA2_REF 0x0C
#define RA0_RA1_ANALOG_RA3_RA2_REF 0x0D
#define RA0_ANALOG 0x0E
#define RA0_ANALOG_RA3_RA2_REF 0x0F
#define RIGHT_JUSTIFIED 0x80
/* Constants used for SETUP_ADC() are: */
#define ADC_OFF 0
#define ADC_START 4
#define ADC_CLOCK_DIV_2 1
#define ADC_CLOCK_DIV_4 0x101
#define ADC_CLOCK_DIV_8 0x41
#define ADC_CLOCK_DIV_16 0x141
#define ADC_CLOCK_DIV_32 0x81
#define ADC_CLOCK_DIV_64 0x181
#define ADC_CLOCK_INTERNAL 0xc1
#define ADC_DONE_MASK 0x04
/********************************************************************* INT
Interrupt Functions: ENABLE_INTERRUPTS(), DISABLE_INTERRUPTS(),
EXT_INT_EDGE()
Constants used in EXT_INT_EDGE() are:
***************************************************************************/
#define L_TO_H 0x40
#define H_TO_L 0
/* Constants used in ENABLE/DISABLE_INTERRUPTS() are: */
#define GLOBAL 0xF2C0
#define INT_RTCC 0xF220
#define INT_TIMER0 0xF220
#define INT_TIMER1 0x9D01
#define INT_TIMER2 0x9D02
#define INT_TIMER3 0xA002
#define INT_EXT 0xF210
#define INT_EXT1 0xF008
#define INT_EXT2 0xF010
#define INT_RB 0xF208
#define INT_AD 0x9D40
#define INT_RDA 0x9D20
#define INT_TBE 0x9D10
#define INT_SSP 0x9D08
#define INT_CCP1 0x9D04
#define INT_CCP2 0xA001
#endif /* 18F252_H */
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Last edited by Mark on Wed Jun 21, 2006 8:36 pm; edited 2 times in total |
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davt
Joined: 07 Oct 2003
Posts: 66
Location: England
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| Posted: Fri Dec 03, 2004 4:40 am |
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Mark
I did not expect the whole program!!
Thanks very much for your expert help - very much appreciated!!
I will get round to implementing it in the new year.
Thanks again - and best wishes for you and yours for Christmas and New Year!!!
Dave |
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davt
Joined: 07 Oct 2003
Posts: 66
Location: England
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| Posted: Thu Dec 09, 2004 9:05 am |
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Hi Mark
Had a bit of spare time - thought I would try your code.
I copied the 18f252_.h into the devices file and created a project.
I then tried to compile, but an error comes up:
" Pic 18f252 *16 unknown type - try PCH "
Any ideas?
Many thanks.
Dave |
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Mark
Joined: 07 Sep 2003
Posts: 2838
Location: Atlanta, GA
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| Posted: Thu Dec 09, 2004 9:55 am |
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| If you are using MPLAB, goto Configure and then Select Device. Choose 18F252. Let me know if it fixes it. |
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davt
Joined: 07 Oct 2003
Posts: 66
Location: England
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| Posted: Thu Dec 09, 2004 10:09 am |
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Mark
I am not using mplab.
Just created a project in CCS compiler version 3.210.
Project created manually device-18f252. |
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Mark
Joined: 07 Sep 2003
Posts: 2838
Location: Atlanta, GA
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| Posted: Thu Dec 09, 2004 10:13 am |
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| I have not ever used the CCS IDE but I know I get that error message when the compiler uses the PCM module when it should be using the PCH. This happens if I select the wrong device. |
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