PIC 18F452 PLL question

[john cutler]

Since I know you would know the answer, I am taking the liberty of writing you sirectly - I hope that's ok with you.

I've been reading oveer the 18F452 data manual and it's not clear to me if it's ok to use an external 10 Mhz clock to drive the Osc#1 pin while i HS-PLL mode to end up with a 40Mhz internal clock. I've seen your posts about crystals with series r, but I have seen nothing on the bbs about an external oscillator. Could ou enlighten me please?

Thanks

John Cutler
verminsky@earthlnk.net
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This message was ported from CCS's old forum
Original Post ID: 10300

[R.J.Hamlett]

:=Since I know you would know the answer, I am taking the liberty of writing you sirectly - I hope that's ok with you.
:=
:=I've been reading oveer the 18F452 data manual and it's not clear to me if it's ok to use an external 10 Mhz clock to drive the Osc#1 pin while i HS-PLL mode to end up with a 40Mhz internal clock. I've seen your posts about crystals with series r, but I have seen nothing on the bbs about an external oscillator. Could ou enlighten me please?
:=
:=Thanks
:=
:=John Cutler
:=verminsky@earthlnk.net
The data sheet does not show this (I know I went looking too...). However, if you think about it logically, the crystal is only acting as a filter, whose output is a signal feeding into the OSC1 pin. I therefore tried the experiment of configuring the chip as 'HS+PLL', and running it off an external oscillator. I got the same problem as I was having with the crystal oscillator, when it was overdriving. I therefore 'tried again', and this time added a series resistor in the line, and a small filter capacitor at the input (22pF, and 180ohms), and got better results (but still not 100\%). Increasing the capacitor to 33pF, resulted in it working OK. However I found 220ohm with 33pF, was also reliable, and I felt gave more margin (I went to this, after finding it all worked, when I attached my scope probe to the input... - this was an 11pF PMK probe). I then tried a small inductor in place of the resistor (4.7uH), and this is the configuration I ended up using.
I found that on some oscillators, the drive was not as agressive, and the lower capacitor value was better.
The 'annoyance' on this, is that you end up with the power penalty of the HS driver still being present (and can't use the extra I/O pins). However it does allow the single clock source, and device synchronisation.
The 'logic' diagram for the PLL driver, shows the oscillator output feeding the PLL phase comparator, but does not show any schmidt trigger symbol on the buffer gate between. My suspicion, is that the buffer is sensitive to the waveshape coming from the oscillator module, and this results in the PLL losing lock, if the shape is not as required. I am slightly hopeful, that MicroChip, may improve the module in latter silicon. I tried the experiment (when initially trying to get this working', of adding a crystal in series with the incoming signal (which should tend to reduce out of band noise on this signal), and this actually proved easier to get working reliably!. In this configuration, the oscillator module is just replacing the OSC2 output, to drive the crystal, and the waveshape is a much purer sinusoid. It appears that the 'critical thing' to getting the PLL working, is to ensure that the incoming signal is sinusoidal, and swinging only about half the rail voltage.

Best Wishes
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This message was ported from CCS's old forum
Original Post ID: 10306