SPI problem

[Thomasn101]

Hi,
If a Master PIC wants to send multiple bytes of data to a Slave PIC (with SS enabled) using SPI, does it have to pull the SS line high at the end of every byte? The slave receives data perfectly with this:
- SS low
- Send data
- Delay 10ms
- SS high
- SS low
- Send data
- Delay 10ms
- SS high

However, The slave doesn't receive data properly with this:
- SS low
- Send data
- Delay 10ms
- Send data
- Delay 10ms
- SS high

Both the slave and the master are F877 @ 20Mhz. Did I do something wrong?
Regards,
Thomas

[Neutone]

The master should puase between bytes but only a very short time. The delay between bytes allows the slave to move bytes into and out of the SPI hardware buffer after each byte finished. Around 10 instruction cycles is plenty usualy. Maybe more if you are loading an array. The SS signals the start of a new packet of data. It allows the slave to be the only recieving device as well as keeping it in sync. Post your code. Get specific help.