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ritchie
Joined: 13 Sep 2003 Posts: 87
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#int_tbe problem |
Posted: Wed Mar 10, 2004 7:57 am |
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Hello,
I have an RS485 system wherein PIN_A1 controls the transmit enable of the MAX485 chip. My concern is that when I check the waveform of my transmit signal it lost one character.. this simply means that PIN_A1 control pin goes low earlier.
How can I resolve this? I use interrupt for transmission and I don't want to use delay on the system. I need your help, suggestions of what algorithm should fit.
Thanx |
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Neutone
Joined: 08 Sep 2003 Posts: 839 Location: Houston
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Posted: Wed Mar 10, 2004 8:32 am |
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I have been using a timer to detect when reception is complete because the pause between bytes has a maximum. I load a timer after each incomming byte. If the timer expires the packet is finished. For transmition I do almost the same thing but instead of setting a flag to decode the packet I turn off the transmit hardware. You can look at the serial file in my home folder that shows this for recieving. It was written for 232 so it is not exactly what you seek but should help you find inspiration. |
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Ttelmah Guest
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Re: #int_tbe problem |
Posted: Wed Mar 10, 2004 8:38 am |
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ritchie wrote: | Hello,
I have an RS485 system wherein PIN_A1 controls the transmit enable of the MAX485 chip. My concern is that when I check the waveform of my transmit signal it lost one character.. this simply means that PIN_A1 control pin goes low earlier.
How can I resolve this? I use interrupt for transmission and I don't want to use delay on the system. I need your help, suggestions of what algorithm should fit.
Thanx |
If I read you correctly, you are setting the TXE, when you first have data available, and then clearing it when the last byte is transferred to TXREG. At this point the problem is that the transmit shift register still contains this byte 'in transit'. You have to consider three possible solutions:
1) External timer - a retriggerable monostable on the TXE line can hold it for a period after you release it in software.
2) Internal delay/timer. Remember you can use an interrupt driven hardware timer. Program this for the character time, when you have no more data to send, and then reset the TXE when this triggers. This removes the need to wait in code.
3) Have the main loop check the transmit shift register status, at intervals, and if it is empty, drop the TXE line.
Best Wishes |
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Gerrit
Joined: 15 Sep 2003 Posts: 58
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Posted: Wed Mar 10, 2004 8:52 am |
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Richie,
Send a copy of your TBE interupt handler this would be easy to answer
your question.
possible :
Depending on the receiver side you can just send a dummy character at the end, or check in your main loop if the TX buffer is empty (TRMT bit).
Gerrit |
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ritchie
Joined: 13 Sep 2003 Posts: 87
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Posted: Wed Mar 10, 2004 5:20 pm |
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Gerrit wrote: | Richie,
Send a copy of your TBE interupt handler this would be easy to answer
your question.
possible :
Depending on the receiver side you can just send a dummy character at the end, or check in your main loop if the TX buffer is empty (TRMT bit).
Gerrit |
Code: |
#int_tbe
void RS485_TXisr() // RS485 transmission interrupt routine
{
// put RFid & keypress data to TX buffer then send?
//fputc(*(TXbuffer+TXout),RS485Com);
TXREG = *(TXbuffer+TXout);
TXout++; // increment TX OUT index
TXout = (TXout) % TX_SIZE; // limit to max buffer size
if (TXin == TXout) // if last in data, stop RS485 TX?
{
disable_interrupts(int_tbe); // stop TX interrupt
RS485_RCV(); // received mode enabled
TXin = 0; // reset TX data IN index
TXout = 0; // reset TX data OUT index
glTXpnd = 0; // reset TX pending flag
}
}
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Gerrit
Joined: 15 Sep 2003 Posts: 58
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Posted: Wed Mar 10, 2004 6:03 pm |
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Hi ritchie,
If you also read the answer of Ttelmah you see the same solution.
If you read specs of usart you find that when the TXREG register gets
empty you get an interrupt, but when TXREG get empty the data is
transfered to the TSR register. Now the compleet character has to be transmitted so you have to start an timer for the time of one character,
or you have to check in your main loop for the TRMT bit. when this bit is
set the real TX buffer is empty.
Good luck
Regards,
Gerrit |
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