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scottc
Joined: 16 Aug 2010
Posts: 95
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| Interrupt on change - Pic18f27k40 |
 Posted: Wed Jan 05, 2022 5:24 am |
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Hi guys.
I have some questions about the IOC function. Looking in the device file it says, // Constants used in ENABLE/DISABLE_INTERRUPTS() are
| Code: |
#define INT_IOC_B2_H2L 0x2104C210
#define INT_IOC_B3_H2L 0x2108C210
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for the pins I am interested in using.
My plan was to use these in a function so as to act on the transition for each of the pins on port B after the processor detected the interrupt. My other thought is that this would provide a more flexible solution to triggering on specific pins as opposed to using something like ext_int_edge(H_TO_L).
My question & it is not clear in the help file is what should appear above the function so as to use these pin defines within the function itself.
I was thinking #INT_EXT, but not too sure.
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#INT_EXT
void IOC_isr() {
{
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Any guidance much appreciated.
Thanks Scott. |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Wed Jan 05, 2022 6:49 am |
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It's in the .h file for the PIC:
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#define INT_EXT2_H2L 0x6002C204
#define INT_EXT2 0x00C204
#define INT_IOC 0x0FFFC210
#define INT_TIMER0 0x00C220
#define INT_AD 0x00C301
#define INT_AD_THRESHOLD 0x00C302
#define INT_CSW 0x00C340 |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19506
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| Posted: Wed Jan 05, 2022 7:46 am |
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And, with the knowledge that this is the Interrupt On Change interrupt,
look at the example ex_ioc.c, which shows how to enable and test which
interrupt has triggered. |
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scottc
Joined: 16 Aug 2010
Posts: 95
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| Posted: Thu Jan 06, 2022 10:22 am |
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Thanks Guys,
The example code was a big help, seems like the #INT_IOC works well.
I like the flexibility of doing the pin assign which I think generally makes using ISR's alot easier and somewhat more predictable. |
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kda406
Joined: 17 Sep 2003
Posts: 97
Location: Atlanta, GA, USA
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| Posted: Tue Jan 18, 2022 11:09 am |
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I could use some elaboration on this topic.
I have the same question as I'm adding a new protocol requiring IOC on B3 on three projects which are using PIC18F26K40 (same as above), 45K40, and 67K40.
The ex_ioc.c example file uses one ISR to service all IOC pins, but there are dozens of IOC capable pins on these processors. It would be too slow to handle all inside one ISR.
Using the 26K40's header as my example, when one wants to use the first serial port, the (vague) header file offers: | Code: | | #define INT_RDA 0x00C520 |
And in the program one creates the ISR like this: | Code: | #INT_RDA
void ui_buff_rx_isr() {
<isr code>
} |
Now here is the problem. The device header file offers this for IOC on B3: | Code: | | #define INT_IOC_B3 0x3108C210 |
However, when I try to use the interrupt in the same manner: | Code: | #INT_IOC_B3
void IOC_B3_ISR(void) {
<isr code>
} |
the compiler balks with the following error: | Quote: | | Error#7 Invalid Pre-Processor directive |
Please tell me I am making a mistake and that I do not have to test for which IOC happened inside my ISR!!!  I plan to add more IOC inputs in the future and change-testing inside the ISR will simply not be fast enough.
Thanks,
Kyle |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19506
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| Posted: Tue Jan 18, 2022 12:00 pm |
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Simple answer, there is only one interrupt for the IOC.
What there are are separate flags set to say which pin has triggered the
interrupt, but you have to poll these flags.
Now the chip does have other interrupts, such as INT on RB0. If you want
separate interrupts you need to switch the using these.Even these though
the separate interrupt handlers are called by polling. There is only one
interrupt vector for _all_ the low priority interrupts, and one other for all
the high priority interrupts. In this vector the code then polls the flags to find
which interrupt has actually triggered. To have separate interrupt vectors
you have to switch to one of the DsPIC's.
Last edited by Ttelmah on Tue Jan 18, 2022 12:05 pm; edited 1 time in total |
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kda406
Joined: 17 Sep 2003
Posts: 97
Location: Atlanta, GA, USA
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| Posted: Tue Jan 18, 2022 12:04 pm |
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That's unfortunate. Thank you for the clarification.
For those who find this thread in the future: This is how the K40 processors actually work. There is one interrupt for change, with flag bits for the individual pins. This is not a limitation of the CCS compiler.
-Kyle |
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