I2C Read failing

robleso7473 · Joined: 25 Mar 2009 Posts: 47

Hello Everyone,

I am using the I2C driver in the dsPIC33CK32MC102 acting as a Master to talk to an FPGA. I use the following: #use i2c(MASTER, I2C1, FAST, RESTART_WDT, stream=I2C_PORT1). This is on dedicated I2C ports RB8/RB9.

The goal is to read internal registers in FPGA by executing the following custom Read sequence using slave address 0x56 followed by a 16-bit memory address 0x0034 and a 16-bit Length byte 0x0001 then I want to read back 4 bytes of data from that location:

Start > 0xAD > 0x0034 > 0x0001 > Read Data1 > Read Data2 > Read Data3 > Read Data4

This is the code:

PCM programmer · Joined: 06 Sep 2003 Posts: 21708

robleso7473 · Joined: 25 Mar 2009 Posts: 47

Thanks for the response.

I will change out the TRUE's to 1's and last one to 0.

I have another question for you, if you please: If this MCU is the master then wouldn't setting it to 1 generate an ack back to the slave? Or does this mean that the MCU(master) will look for an ack from the slave. It's a bit confusing to me.

thanks again!
Oscar

PCM programmer · Joined: 06 Sep 2003 Posts: 21708

When reading from an i2c slave, the master is the device that
sends an ACK or a NACK to the slave.

More explanation:
https://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus/i2c-bus-events/giving-acknowledge-to-a-slave-device.html

Ttelmah · Joined: 11 Mar 2010 Posts: 19515

I2C, by using an 'open collector' drive, supports transfers in both directions
on each wire.
So the ''slave', can hold the clock from releasing to delay the master
(clock stretch). Then the master can receive data, by commanding the
slave to send, and sending the clocks, while the slave then drives the data
line to give data to the master. In I2C, all transfers have a ACK or NACK,
which is generated by the receiving device. So when the master is receiving,
it is the master that must ACK/NACK.
For transmissions it is the slave that sends this. For reception, it is the
master.
The rmaster device, when receiving, 'ACK's all but the last byte. This byte
has a NACK. This is a marker to the slave device to say that this is the end
of the packet. It is this that releases the toggle in the slave device to switch
it back to receiving.
Many slaves will automatically reset this, when they see a 'stop'. However
a lot do not. On any device where this is not done, not sending this last
NACK, can result in the slave state machine becoming stuck.....

robleso7473 · Joined: 25 Mar 2009 Posts: 47

Thanks for this additional insight.
Much appreciated fellows.
Oscar

robleso7473 · Joined: 25 Mar 2009 Posts: 47

I'm back!

I still have an issue when executing a read command where after the high address byte below the MCU will not send out the next byte 0x34, it simply ignores the next 3 writes to 0x34, 0x00 and 0x01 and goes straight into reading data1 and data0.

Is the I2C Read function designed to only push out one 8-bit address value prior to clocking back data?

i2c_start();
i2c_write(0xAD); // I2C slave address + write address
i2c_write(0x00); // Write high address byte
i2c_write(0x34); // Write low address byte
i2c_write(0x00); // Write Length byte 1
i2c_write(0x01); // Write Length byte 0
data1 = i2c_read(1); // Read data byte 1
data0 = i2c_read(1); // Read data byte 0
i2c_stop();
}

I want to post an image of the I2C transaction from my Saleae logic analyzer but don't know how to paste it on here - can you help?

Thanks for support,
Oscar

Ttelmah · Joined: 11 Mar 2010 Posts: 19515

This is where a restart is used.

The sequence has to be:

start
write device address set to write.
write the register addresses (however many bytes are needed)
trigger a 'restart' (send a start without a stop)
write the device address set to read
Now read the bytes nacking the last one.
stop.

The point is that after an address is sent with the 'read' flag, only reads
are allowed. To set a address you have to do a write transaction, then
turn the bus around with the restart, and the read flag.

To your question: