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pmuldoon
Joined: 26 Sep 2003
Posts: 218
Location: Northern Indiana
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| 16f18326 CCP timer question |
 Posted: Mon Jan 07, 2019 8:52 am |
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16f18326 CCP timer
I'm reading the datasheet and not sure how to interpret this note:
section 29.2.2
| Quote: | Clocking Timer1/3/5 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1/3/5 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source. |
I'm using Timer1 clocked off of Fosc at 16MHz. The CCP Capture is fired from the internal Comparator output.
Is this saying I need to clock the timer from Fosc/4 instead of Fosc or is that just for when you're using an external pin as the capture trigger?
CCP can also be clocked off of Timer0, and the note doesn't say anything about it not being able to run IT at Fosc. Would that be a safer choice?
I caught this note late in the dev process and have found a little noise on the CCP result which seems too small to be caused by this issue and is otherwise working fine-probably comparator threshold, ref noise. Any theories on what kind of problem you'd run into running the timer at Fosc in CCP mode? It seems like the counter should increment okay, and the ccp trigger should (?) latch both hi/lo regs simultaneously. After that, reading the regs should be no problem.
Again, it does seem to be working okay, I'm just not clear on if the note applies. |
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pmuldoon
Joined: 26 Sep 2003
Posts: 218
Location: Northern Indiana
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| Posted: Mon Jan 07, 2019 10:33 am |
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I found an app note:
AN1473 Various Solutions for Calculating
a Pulse and Duty Cycle
It seems to confirm I screwed up. That there is a limitation with the CCP that isn't a problem when using the gated timer mode. I think I can change to a gated timer technique instead of using the CCP. Apparently the limitation is only with the CCP.
Again, it DOES seem to be working, so maybe I am losing resolution and don't realize it because I don't need the extra resolution.
More fun stuff to look into... |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19513
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| Posted: Mon Jan 07, 2019 10:51 am |
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You should be OK.
Reason is that the comparator output is synchronised to the Q1 state.
The problem comes when a capture event triggers 'mid instruction', and
the timer is being clocked at a faster rate than the instruction clock.
This can result in the event being missed.
If you look at the comparator block diagram, the comparator output
is clocked by Q1, so should only ever happen on the Q1 instruction state.
However you don't actually gain anything by clocking at the faster rate.
Because the comparator output can only trigger once per instruction
the faster clock won't give more resolution.... |
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pmuldoon
Joined: 26 Sep 2003
Posts: 218
Location: Northern Indiana
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| Posted: Mon Jan 07, 2019 11:08 am |
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That makes sense. So even though I didn't have the resolution I thought I did, my testing seems to show that the results were fine, anyway. I'll set the timer clock to Fosc/4 and see if my accuracy stays the same. I may kick the osc up from 16MHz to 32MHz too, just to see what happens.
But...If that were all true it seems like my timer counts would have to always be in increments of 4 counts. The timer has to be reset on an Fosc/4 cycle and the comparator triggers on an Fosc/4 cycle. I will do a little testing tomorrow and look specifically at that as well.
Thanks, |
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pmuldoon
Joined: 26 Sep 2003
Posts: 218
Location: Northern Indiana
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| Posted: Mon Jan 07, 2019 11:51 am |
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I'm busy with something else today, so I can't do any testing at the moment, but I looked again at the comparator and my setup:
| Code: |
setup_timer_1(T1_INTERNAL | T1_FOSC);
setup_comparator(CP1_C1_DAC | CP1_INT_H2L); |
I have it setup so it is not sync'd (nor is it in fast mode).
And in looking at the Tmr1 and Comp diagrams, It looks like the signal would latch a flipflop and propagate thru just a few gates to the enable of the clock. I'm just not seeing where the problem or limitation is. |
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