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PIC 18F23K22

 
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JAM2014



Joined: 24 Apr 2014
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PIC 18F23K22
PostPosted: Mon Oct 31, 2016 9:48 am     Reply with quote

Hi All,

I'm considering the PIC 18F23K22 for an upcoming project as I'll need 2 hardware UART's. It appears, however, that the pins for UART2 are shared with the ICSP pins on the SOIC28 package..... UART2 will be connected to an Xbee modem, so I assume I'll have to isolate the Xbee modem during programing by removing it, or adding isolation jumpers? Neither solution is particularly appealing, which makes me wonder why Microchip designed the chip like this?

Another option, I guess, would be to bite the bullet and use the QFN package instead which does not have this conflict.

How do others address this situation?

Jack
newguy



Joined: 24 Jun 2004
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PostPosted: Mon Oct 31, 2016 11:16 am     Reply with quote

I just avoid the package that has the conflict, if another conflict-free package is available.

If the QFN package is what scares you, that tells me that you're prototyping this yourself. If that's the case, do yourself a favour and purchase a hot air pencil and solder paste. You can get decent quality, very inexpensive hot air reflow tools on ebay. The solder paste can be obtained from digikey or mouser or others.

Once you try mounting or removing components with a hot air system you'll wonder why you didn't go with one sooner.

You can even get inexpensive IR reflow ovens on ebay too if you're worried about handheld tools.
temtronic



Joined: 01 Jul 2010
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PostPosted: Mon Oct 31, 2016 11:33 am     Reply with quote

bigger IS better ! I don't see any good reason to use itty bitty PICs,especially if making in the 'home'. There's more to consider than just the 'per PIC' cost.
I settled on the 18F46K22 for 90% of all projects.haven't run out of PICs no matter what the clients ask for AFTER the POC tests.
I will be using the 28pin 'baby' for some WOTSUP projects this winter though.

Jay
PCM programmer



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PostPosted: Mon Oct 31, 2016 11:39 am     Reply with quote

If you're willing to use an SOIC-28, you could just go to the next larger
size PIC and use TQFP-44. That's because the courtyard for the SOIC-28
package is 17.9 x 11.4 mm. For the TQFP-44 it's 12.9 mm square.
The courtyard, as I referring to it, is the largest dimension of either the
ends of the pcb pads or the package, in the X,Y directions.

In terms of area, the SOIC-28 uses 204 sq. mm vs. 166 sq. mm for the
TQFP. The TQFP-44 is actually less area, in a leaded package. Though
it does cost more.
Ttelmah



Joined: 11 Mar 2010
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PostPosted: Mon Oct 31, 2016 1:03 pm     Reply with quote

And as for 'why', simple. Look at the pins on the chip. The ICSP, has to go to pins that are not used for analog. Problem is that there are so few on the 28pin package. All are used by something else (CCP, PWM, oscillator etc..).
This is why the slightly better models above this chips have more peripherals relocatable, so the choice becomes yours.
JAM2014



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PostPosted: Mon Oct 31, 2016 8:26 pm     Reply with quote

Hi All,

Thanks for all the thoughtful insight guys! I've decided to go with the 44 lead QFP package part and avoid any pin conflicts. My initial hesitation to go this route was not really about the package itself, although it is a one-off prototype, but rather that it seemed like the 44 lead part was way overkill for this project. In the end, what does it matter when the part cost is not a factor and board area is ample?

Thanks,

Jack
Ttelmah



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PostPosted: Tue Nov 01, 2016 3:39 am     Reply with quote

And, add that you may well find it possible to simplify the layout/code, using the larger chip.
For instance, if you have a device that requires 8 bits, on the 28pin package, it is unlikely that you will be able to get a whole 'port' free, so end up having to use bits from more than one port, when on the larger chip, you may well be able to make this is a single port connection, which then make the I/O simpler to code. Smile
Similarly when laying out the board, first route the stuff that is 'fixed' (so the ICSP, serials etc.), then you may be able once this is done to use pins on the side of the chip closest to the devices being controlled, and make the board layout easier.
Nothing is worse than having all the pins used, and then using devices that are in the most inconvenient locations round the chip possible....
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