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Message |
pran
Joined: 10 Sep 2015
Posts: 4
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| problem with nrf24l01+ code |
 Posted: Thu Sep 17, 2015 4:04 am |
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Hi all. I have got a doubt with the code i got from code library for nrf24l01+. I am having doubt in the particular function used in the code.
| Code: |
void configure_RX()
{
int i;
RX_CSN_Low();
RX_CE_Low();;
bb_xfer(W_REGISTER); //PRX, CRC enabled
bb_xfer(0x39); //data 0b0011 1001
pulse_CSN();
delay_ms(2);
//-----------
bb_xfer(0x21); //disable auto-ack for all channels
bb_xfer(0x00); ///
pulse_CSN();
//-----------
bb_xfer(0x23); //address width = 5 bytes
bb_xfer(0x03);
pulse_CSN();
//-----------
bb_xfer(0x26); //data rate = 1MB
bb_xfer(0x07);
pulse_CSN();
//-----------
bb_xfer(0x31); //4 byte payload
bb_xfer(0x04);
pulse_CSN();
//-----------
bb_xfer(0x25); //set channel 2
bb_xfer(0x02);
pulse_CSN();
//-----------
bb_xfer(0x30); //set address E7E7E7E7E7
for(i=0;i<=5;i++)
{
bb_xfer(0xe7); // send 5 bytes of data E7 E7 E7 E7 E7
}
pulse_CSN();
//----------------
bb_xfer(0x20); //PWR_UP = 1
bb_xfer(0x3b);
RX_CSN_High();;
RX_CE_High();
}
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When we are writing something to registers of nrf24l01+, isn't it required that we send command "W_REGISTER" followed by the register bits? But in the code given above,
| Code: |
bb_xfer(W_REGISTER); //PRX, CRC enabled
bb_xfer(0x39); //data 0b0011 1001
pulse_CSN();
delay_ms(2);
//-----------
bb_xfer(0x21); //disable auto-ack for all channels
bb_xfer(0x00); ///
pulse_CSN();
//-----------
bb_xfer(0x23); //address width = 5 bytes
bb_xfer(0x03);
pulse_CSN();
//-----------
|
the W_REGISTER command is sent only once.
Finally what does these two lines do?
| Code: |
bb_xfer(0x21);
bb_xfer(0x00);
|
What is the data being sent in these lines?
Please help if anyone knows about this.
Thanking you in advance. |
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drolleman
Joined: 03 Feb 2011
Posts: 116
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| Posted: Thu Sep 17, 2015 9:48 pm |
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| This is an old part the manufacturer states "not for new designs" its last docs are 2007. You are better to use a part that has ccs code already done, to get started. Then modify it for your use. |
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pran
Joined: 10 Sep 2015
Posts: 4
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| Posted: Fri Sep 18, 2015 10:49 am |
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| Ok .Thanks ,drolleman.Do you have any links for already done ccs code for nrf24l01+? |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Fri Sep 18, 2015 8:48 pm |
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| Quote: |
bb_xfer(W_REGISTER); //PRX, CRC enabled
bb_xfer(0x39); //data 0b0011 1001
pulse_CSN();
delay_ms(2);
//-----------
bb_xfer(0x21); //disable auto-ack for all channels
bb_xfer(0x00); ///
pulse_CSN();
//-----------
bb_xfer(0x23); //address width = 5 bytes
bb_xfer(0x03);
pulse_CSN();
//-----------
the W_REGISTER command is sent only once.
|
Actually, it's being sent every time. Look at page 48 of the nRF24L01+
data sheet. It shows the format of the Write Register (W_REGISTER)
command is: 001a aaaa, where "aaaaa" is a 5-bit register address.
The upper 3 bits are set to 001, which is the Write Register command.
In hex notation, this is 0x2-something.
Now look closely at the code above, at the sections in bold. The 2nd and
3rd sections both begin with an SPI transfer to address 0x2-. The 0x2 in
the high nybble is the Write Register command. The address fields are 1
and 3, respectively.
So it is doing a Write Register each time. First it writes to register 0,
then to register 1, and then to register 3. The coding method is kind
of sloppy. He should have used defined constants instead of magic
numbers like 0x21 and 0x23.
This is also true for his magic number of 0x31. The top 3 bits are still
001 (in binary), therefore 0x31 is a Write Register command to register
address 0x11. |
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drolleman
Joined: 03 Feb 2011
Posts: 116
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| Posted: Sat Sep 19, 2015 11:38 am |
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| no what I was saying was use a newer chip, that has code |
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