EEPROM life extension

rikotech8 · Joined: 10 Dec 2011 Posts: 376 Location: Sofiq,Bulgariq

Hello guys.
I have the following problem:
On my board I have 24LC256 eeprom with 1000 000 erase/write cycles.
In the worst case I will be overwriting 6400 times per hour. According to my calculation the eeprom will be operational for at least 156 hours (not long enough). But if I write each time to a different memory location it will extend the eeprom life 32 000 times which is long enough time. I would like to let you know that the eeprom is not used for any other data and all the eeprom space is available for this purpose. Is there a well known software approach to use the complete memory space for small amount of data, but each time located at different eeprom addresses. The problem is (after reset) how would I know where (at what eeprom address) the last data is written to, or where the first empty address is so I can write there?
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Ttelmah · Joined: 11 Mar 2010 Posts: 19454

Honestly, simplest answer, switch to an FRAM.....
No write life limits. Smile

Answer generically, depends on the values you need to use. Normal method is to use an extra cell for each number.
EEPROM erases to 0xFF (normally).

So use one byte as a flag. ==0xFF > entry is unused
== 0xAA > entry is latest and in use
== 0x00 > entry is historical

Then have however many bytes your value needs following this (1,2,3 etc..), to the next value.

If (for instance) your value needed three bytes, then you would have a four byte 'record' with this flag as the first byte in each.

Then you can scan the EEPROM for the first record that has 0xFF as it's flag, and this is then the next location to write. The entry with 0xAA as it's flag is the last one written, and the entries with 0, are the historical data.

dyeatman · Joined: 06 Sep 2003 Posts: 1932 Location: Norman, OK

Why put yourself through this.
Why not FRAM? Drop in replacement, longer life and FASTER!

(looks like TTelmah beat me to the punch...)
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temtronic · Posted: Sat Jun 06, 2015 5:00 am

You don't say how much data you're updating(1 byte, 4 bytes, 100 ?) however you do mention per hour. Assuming you have an RTC chip for timekeeping, use its battery backed CMOS RAM. Unlimited R/W, already there,easy to use,faster than the onboard EEPROM of the PIC.
I assuming you're 'updating' the same data 6400 times per hour NOT 'datalogging' the data.

options, you always need options.
Jay

newguy · Joined: 24 Jun 2004 Posts: 1907

Actually FRAM does have a life limit. At my present employer, we've found it (or it found us).

Our main human interface product has an 8k FRAM, and the original boards dated from ~1998. About 4 years ago (so about 13 years in service), some of these boards started failing uploads of new config data. What we were seeing was some memory locations with sticky bits that wouldn't change state.

At that point we started changing all the FRAMs for a different manufacturer. Original was Ramtron, not sure what the new one is, but it's definitely not Ramtron. About the same time we had issues, Ramtron quietly pulled all their FRAM memory ICs from the market only to reappear with slightly different model numbers a couple of years later. Made me suspicious.

I've also long suspected the software that actually reads/writes those FRAMs too, as the driver was poorly written. A change of a single bit is handled by a write of a 64 byte page instead of a single byte. Always hated that, but too difficult to go back and rework it to be more intelligent at this point in time.

drh · Posted: Sat Jun 06, 2015 8:56 am

newguy · Joined: 24 Jun 2004 Posts: 1907

I know. The replacement isn't a Cypress/Ramtron part.

Ttelmah · Joined: 11 Mar 2010 Posts: 19454

Toshiba also do FRAM.

However you were almost certainly hitting a chip life limit, rather than an FRAM limit.

All chips have a life limit, as do capacitors (worst), resistors, transistors etc.. The point about FRAM is that it's limit is determined by conventional IC ageing, rather than the much faster processes in the EEPROM.

So you hit an age limit, not a number of cycles limit.

I've had PROM's (yes the fuse based memories), die from this....

asmboy · Joined: 20 Nov 2007 Posts: 2128 Location: albany ny

i would not hesitate to use a Microchip
23LC512 64kx8bit 32byte page fully static ram
with a coin-cell and BAT54-A power sharing diode such that the coin cell is just
drawing about 500nA when the PIC VDD is absent.

SPI clock of 20mhz ok......

best of all it is an 8 pin dip pin compatible with many popular EEProms.

no read write limits at all -lightning fast with NO write delays at all.
smokes every NV ram hands down.........

newguy · Joined: 24 Jun 2004 Posts: 1907

Ttelmah · Joined: 11 Mar 2010 Posts: 19454

A batch failure can happen with anything. Your timing sounds like it might well be a problem like poor sealing on the legs.
I had to destroy over 250000 PIC's at one point following thousands of failures in only a few weeks (Microchip did eventually replace these).

I suspect that this may well reflect part of the reason that Ramtron were sold. However the technology is supported by lots of other companies.

Fujitsu, Cypress (now), Texas & Toshiba (that I know of), then several smaller specialist manufacturers.

The Texas data gives life as > 1E15 cycles, which is the same figure they give for SRAM.