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prasad_21
Joined: 12 Nov 2014
Posts: 11
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| PIC18LF14K22 interface with ADF7021 transceiver |
 Posted: Tue Feb 17, 2015 2:31 am |
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| I am working on RF communication using ADF7021 and PIC18LF14K22 but CCS does not have inbuilt driver for ADF. Please help me with the driver file for the same. Thanks. |
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temtronic
Joined: 01 Jul 2010
Posts: 9161
Location: Greensville,Ontario
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| Posted: Tue Feb 17, 2015 6:21 am |
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That device is a 48pin SMT and requires a LOT of expert PCB designing to get it to operate correctly, so I assume you are using a 'module' and not the SMT chip?
If so, then I'd download AD's PDF of their 'demo kit'. It has a lot of the details in it.
This is NOT an easy project for a beginner though with a LOT of reading and a LOT of code cutting, you might be able to get them to work in a month or so.
Step 1, get a PIC to run the 1Hz LED program
Step 2, get a PIC to 'talk' to a PC
Step 3, get 2 PICs to 'communicate' via RS232 hardwired
Step 4, cut code to have a PIC access the xcvr
Step 5, cut code to have PICs use AD xcvr.
You must breakdown the project into small, simple steps, building on what works (and doesn't). RF communications is 'tricky' and involves a LOT of reading and testing.
good luck
Jay |
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dyeatman
Joined: 06 Sep 2003
Posts: 1923
Location: Norman, OK
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| Posted: Tue Feb 17, 2015 9:53 am |
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One thing that you have to decide is which interface will you use?
You have a number to choose from SPI, I2C, RS232 etc.
After you confirm the PIC is working correctly, establishing comms with
the chip will be relatively easy. On the other hand, setting up the chip
is quite a bit harder.
_________________
Google and Forum Search are some of your best tools!!!! |
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prasad_21
Joined: 12 Nov 2014
Posts: 11
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| Posted: Wed Feb 18, 2015 11:56 pm |
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@temtronic
Thanks for your reply. I am using a module which is in working condition i.e. i already have a proven hardware ready to use and only need to write the firmware and establish communication between adf and pic, the first 3 steps stated by you have already been done. I need a driver file of ADF for an SPI communication to be established. As far as the ready demo kit of ADF is concerned it is just the hardware which is available and again the firmware is to be established so i decided to go ahead with the hardware which i already have. |
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prasad_21
Joined: 12 Nov 2014
Posts: 11
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| Posted: Thu Feb 19, 2015 12:02 am |
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@dyeatman
I have decided to choose SPI interface and have confirmed the working status of PIC. Now my concern is to establish communication for which i have taken help of google and various forums but i am not getting the help required. Kindly help me with the driver of ADF with initialization of registers. Thanks. |
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prasad_21
Joined: 12 Nov 2014
Posts: 11
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| Posted: Sat Feb 28, 2015 3:12 am |
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| Can anyone please help me with the driver? I am stuck. Thanks.. |
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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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| Posted: Sun Mar 01, 2015 10:39 am |
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i suggest you post the code you have done so far.
include information on the frequency band you want to use
and data formats you propose to transfer.
as of now, you have not shown us anything to know how badly
"stuck" you really are.
keep in mind that
nobody on the forum is going to write a driver for you - |
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prasad_21
Joined: 12 Nov 2014
Posts: 11
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| Posted: Mon Mar 09, 2015 3:56 am |
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@asmboy
Thanks for your suggestion..
Please find below the code i have written so far.. And as far the problem is concerned i have no idea which register configurations should be chosen for my application and why, but still i have assumed some default configurations and written the code, so was wanting help for the same. I have it in mind that nobody is going to write a driver for me.
Frequency:869MHz
Data Format: Binary
| Code: | #ifndef ADF_SELECT
#define ADF_SELECT PIN_C0 //C1
#define ADF_CLK PIN_C3
#define ADF_DI PIN_C2 //mosi
#define ADF_DO PIN_C4 //miso
#endif
#define N_REGISTER_0 0
#define VCO_OSCILLATOR_REGISTER_1 1
#define TRANSMIT_MODULATION_REGISTER_2 2
#define TRANSMIT_RECEIVE_CLOCK_REGISTER_3 3
#define DEMODULATOR_SETUP_REGISTER_4 4
#define IF_FILTER_SETUP_REGISTER_5 5
#define IF_FINE_CAL_SETUP_REGISTER_6 6
#define READBACK_SETUP_REGISTER_7 7
#define POWER_DOWN_TEST_REGISTER_8 8
#define AGC_REGISTER_9 9
#define AFC_REGISTER_10 10
#define SYNC_WORD_DETECT_REGISTER_11 11
#define SWD_THRESHOLD_SETUP_REGISTER_12 12
#define FSK_3_4FSK_DEMOD_REGISTER_13 13
#define TEST_DAC_REGISTER_14 14
#define TEST_MODE_REGISTER_15 15
/*********************************************************************************/
/********* define N_REGISTER_0 ************************/
#define BIT_8_INTEGER_N 44
#define BIT_15_FRACTIONAL_N_Tx 5961
#define BIT_15_FRACTIONAL_N_Rx 5794
/*** MUXOUT_CONTROL ***/
#define REGULATOR_READY (0x0<<29)
#define FILTER_CAL_COMPLETE (0x1<<29)
#define DIGITAL_LOCK_DETECT (0x2<<29)
#define RSSI_READY (0x3<<29)
#define Tx_Rx (0x4<<29)
#define LOGIC_ZERO (0x5<<29)
#define TRISTATE (0x6<<29)
#define LOGIC_ONE (0x7<<29)
#define UART_MODE_EN (0x1<<28)
#define TRANSMIT (0x0<<27)
#define RECEIVE (0x1<<27)
#define INTEGER_N (BIT_8_INTEGER_N<<19)
#define FRACTIONAL_N_Tx (BIT_15_FRACTIONAL_N_Tx<<4)
#define FRACTIONAL_N_Rx (BIT_15_FRACTIONAL_N_Rx<<4)
/**********************************************************************************/
/********* define VCO_OSCILLATOR_REGISTER_1 ****************************/
#define BIT_4_VCO_BIASCURRENT 10
#define BIT_2_CP_CURRENT 2
#define BIT_2_XTAL_BIAS 2
#define BIT_4_CLOCKOUT_DIVIDE 0
#define BIT_3_R_COUNTER_DIVIDE_RATIO 1
#define EXTERNAL_L_VCO (0x1<<25)
//VCO CENTER FREQ ADJUST
#define NOMINAL (0x0<<23)
#define VCO_ADJUST_UP_1 (0x1<<23)
#define VCO_ADJUST_UP_2 (0x2<<23)
#define VCO_ADJUST_UP_3 (0x3<<23)
//VCO_BIAS
#define VCO_BIASCURRENT (BIT_4_VCO_BIASCURRENT<<19)
#define RF_DIVIDE_BY_2 (0x1<<18)
#define VCO_LOOP_CONDITION_ON (0x1<<17)
#define CP_CURRENT (BIT_2_CP_CURRENT<<15)
#define XTAL_BIAS (BIT_2_XTAL_BIAS<<13)
#define XOSC_ENABLE (0x1<<12)
#define XTAL_DOUBLER (0x1<<11)
#define CLOCKOUT_DIVIDE (BIT_4_CLOCKOUT_DIVIDE<<7)
#define R_COUNTER_DIVIDE_RATIO (BIT_3_R_COUNTER_DIVIDE_RATIO<<4)
/**********************************************************************************/
/********* define TRANSMIT_MODULATION_REGISTER_2 ************************/
#define BIT_9_Tx_FREQUENCY_DEVIATION 7
#define BIT_6_POWER_AMPLIFIER 46
#define BIT_2_PA_BIAS 2
#define BIT_3_PA_RAMP 1
#define RAISED COSINE ALPHA (0x1<<30)
//TxDATA INVERT
#define TxINVERT_NORMAL (0x0<<28)
#define TxINVERT_CLK (0x1<<28)
#define TxINVERT_DATA (0x2<<28)
#define TxINV_CLK_AND_DATA (0x3<<28)
#define Tx_FREQUENCY_DEVIATION (BIT_9_Tx_FREQUENCY_DEVIATION<<19)
#define POWER_AMPLIFIER (BIT_6_POWER_AMPLIFIER<<13)
#define PA_BIAS (BIT_2_PA_BIAS<<11)
#define PA_RAMP (BIT_3_PA_RAMP<<8)
#define PA_ENABLE (0x1<<7)
//MODULATION_SCHEME
#define FSK_2 (0x0<<4)
#define GAUSSIAN_2FSK (0x1<<4)
#define FSK_3 (0x2<<4)
#define FSK_4 (0x3<<4)
#define OVERSAMPLED_2FSK (0x4<<4)
#define RAISED_COSINE_2FSK (0x5<<4)
#define RAISED_COSINE_3FSK (0x6<<4)
#define RAISED_COSINE_4FSK (0x7<<4)
/**********************************************************************************/
/********* define TRANSMIT_RECEIVE_CLOCK_REGISTER_3 ********************/
#define BIT_6_AGC_CLK_DIVIDE 10
#define BIT_8_SEQUENCER_CLK_DIVIDE 197
#define BIT_8_CDR_CLK_DIVIDE 38
#define BIT_4_DEM_CLK_DIVIDE 4
#define BIT_2_BBOS_CLK_DIVIDE 2
#define AGC_CLK_DIVIDE (BIT_6_AGC_CLK_DIVIDE<<26)
#define SEQUENCER_CLK_DIVIDE (BIT_8_SEQUENCER_CLK_DIVIDE<<18)
#define CDR_CLK_DIVIDE (BIT_8_CDR_CLK_DIVIDE<<10)
#define DEM_CLK_DIVIDE (BIT_4_DEM_CLK_DIVIDE<<6)
#define BBOS_CLK_DIVIDE (BIT_2_BBOS_CLK_DIVIDE<<4)
/***********************************************************************************/
/********* define DEMODULATOR_SETUP_REGISTER_4 ********************/
#define BIT_10_POST_DEMOD_BW 4
#define BIT_10_DISCRIMINATOR_BW 590
//IF_BW
#define IF_BW_12_5kHz (0x0<<30)
#define IF_BW_18_75kHz (0x1<<30)
#define IF_BW_25kHz (0x2<<30)
#define IF_BW_INVALID (0x3<<30)
#define POST_DEMOD_BW (BIT_10_POST_DEMOD_BW<<20)
#define DISCRIMINATOR_BW (BIT_10_DISCRIMINATOR_BW<<10)
//Rx_NVERT
#define Rx_INVERT_NORMAL (0x0<<8)
#define Rx_INVERT_CLK (0x1<<8)
#define Rx_INVERT_DATA (0x2<<8)
#define Rx_INVERT_CLK_DATA (0x3<<8)
#define DOT_PRODUCT (0x1<<7)
//DEMOD_SCHEME
#define DEMOD_SCHEME_2FSK_LINEAR (0x0<<4)
#define DEMOD_SCHEME_2FSK_CORRELATOR (0x1<<4)
#define DEMOD_SCHEME_3FSK (0x2<<4)
#define DEMOD_SCHEME_4FSK (0x3<<4)
/***********************************************************************************/
/********* define IF_FILTER_SETUP_REGISTER_5 ********************/
#define BIT_5_IR_GAIN_ADJUST_MAG 0
#define BIT_4_IR_PHASE_ADJUST_MAG 0
#define BIT_6_IF_FILTER_ADJUST 0
#define BIT_9_IF_FILTER_DIVIDER 392
#define IR_GAIN_ADJUST_UP_DN (0x1<<31)
#define IR_GAIN_ADJUST_Q (0x1<<30)
#define IR_GAIN_ADJUST_MAG (BIT_5_IR_GAIN_ADJUST_MAG<<25)
#define IR_PHASE_ADJUST_Q (0x1<<24)
#define IR_PHASE_ADJUST_MAG (BIT_4_IR_PHASE_ADJUST_MAG<<20)
#define IF_FILTER_ADJUST (BIT_6_IF_FILTER_ADJUST<<14)
#define IF_FILTER_DIVIDER (BIT_9_IF_FILTER_DIVIDER<<5)
#define IF_CAL_COARSE (0x1<<4)
/***********************************************************************************/
/********* define IF_FINE_CAL_SETUP_REGISTER_6 ********************/
#define BIT_7_IF_CAL_DWELL_TIME 40
#define BIT_8_IF_CAL_UPPER_TONE_DIVIDE 75
#define BIT_8_IF_CAL_LOWER_TONE_DIVIDE 150
#define IR_CAL_SOURCE_+_2 (0x1<<30)
//IR CAL SOURCEDRIVE LEVEL
#define IR_CAL_SOURCEDRIVE_LEVEL_OFF (0x0<<28)
#define IR_CAL_SOURCEDRIVE_LEVEL_LOW (0x1<<28)
#define IR_CAL_SOURCEDRIVE_LEVEL_MED (0x2<<28)
#define IR_CAL_SOURCEDRIVE_LEVEL_HIGH (0x3<<28)
#define IF_CAL_DWELL_TIME (BIT_7_IF_CAL_DWELL_TIME<<21)
#define IF_CAL_UPPER_TONE_DIVIDE (BIT_8_IF_CAL_UPPER_TONE_DIVIDE<<13)
#define IF_CAL_LOWER_TONE_DIVIDE (BIT_8_IF_CAL_LOWER_TONE_DIVIDE<<5)
#define IF_FINE_CAL (0x1<<4)
/***********************************************************************************/
/********* define READBACK_SETUP_REGISTER_7 ********************/
#define READBACK_ENABLED (0x1<<8)
//READBACK MODE
#define AFC_WORD (0x0<<6)
#define ADC_OUTPUT (0x1<<6)
#define FILTER_CAL (0x2<<6)
#define SILICON_RE (0x3<<6)
//ADC MODE
#define MEASURE_RSSI (0x0<<4)
#define BATTERY_VOLTAGE (0x1<<4)
#define TEMP_SENSOR (0x2<<4)
#define TO_EXTERNAL_PIN (0x3<<4)
/***********************************************************************************/
/********* define POWER_DOWN_TEST_REGISTER_8 ********************/
#define COUNTER RESET (0x1<<15)
#define CDR_RESET (0x1<<14)
#define DEMOD_RESET (0x1<<13)
#define PA_ENABLE_Rx_MODE (0x1<<12)
#define Tx/Rx_SWITCH_ENABLE (0x1<<11)
#define LOG_AMP_ENABLE (0x1<<10)
#define DEMOD_ENABLE (0x1<<9)
#define ADC_ENABLE (0x1<<8)
#define FILTER_ENABLE (0x1<<7)
#define LNA/MIXER_ENABLE (0x1<<6)
#define SYNTH_ENABLE (0x1<<4)
/***********************************************************************************/
/********* define AGC_REGISTER_9 ********************/
#define BIT_7_AGC_HIGH_THRESHOLD 70
#define BIT_7_AGC_LOW_THRESHOLD 30
#define MIXER_LINEARITY_HIGH (0x1<<28)
#define LNA_CURRENT (0x0<<26)
#define LNA_MODE_REDUCED GAIN (0x1<<25)
#define FILTER_CURRENT_HIGH (0x1<<24)
#define FILTER_GAIN_8 (0x0<<22)
#define FILTER_GAIN_24 (0x1<<22)
#define FILTER_GAIN_72 (0x2<<22)
#define FILTER_GAIN_INVALID (0x3<<22)
#define LNA_GAIN_3 (0x0<<20)
#define LNA_GAIN_10 (0x1<<20)
#define LNA_GAIN_30 (0x2<<20)
#define LNA_GAIN_INVALID (0x3<<20)
//AGC_MODE
#define AUTO_AGC (0x0<<18)
#define MANUAL_AGC (0x1<<18)
#define FREEZE_AGC (0x2<<18)
#define AGC_HIGH_THRESHOLD (BIT_7_AGC_HIGH_THRESHOLD<<11)
#define AGC_LOW_THRESHOLD (BIT_7_AGC_LOW_THRESHOLD<<4)
/***********************************************************************************/
/********* define AFC_REGISTER_10 ********************/
#define BIT_8_MAX_AFC_RANGE 50
#define BIT_3_KP 4
#define BIT_4_KI 11
#define BIT_12_AFC_SCALING_FACTOR 426
#define MAX_AFC_RANGE (BIT_8_MAX_AFC_RANGE<<24)
#define KP (BIT_3_KP<<21)
#define KI (BIT_4_KI<<17)
#define AFC_SCALING_FACTOR (BIT_12_AFC_SCALING_FACTOR<<5)
#define AFC_EN (0x1<<4)
/***********************************************************************************/
/********* define SYNC_WORD_DETECT_REGISTER_11 ********************/
#define BIT_24_SYNC_BYTE_SEQUENCE 0xFAAAAE
#define SYNC_BYTE_SEQUENCE (BIT_24_SYNC_BYTE_SEQUENCE<<8)
//MATCHINGTOLERANCE
#define ACCEPT_0_ERRORS (0x0<<6)
#define ACCEPT_1_ERROR (0x1<<6)
#define ACCEPT_2_ERRORS (0x2<<6)
#define ACCEPT_3_ERRORS (0x3<<6)
//SYNC_BYTE_LENGTH
#define SYNC_12_BITS (0x0<<4)
#define SYNC_16_BITS (0x1<<4)
#define SYNC_20_BITS (0x2<<4)
#define SYNC_24_BITS (0x3<<4)
/***********************************************************************************/
/********* define SWD_THRESHOLD_SETUP_REGISTER_12 ********************/
#define BIT_8_DATA_PACKET_LENGTH 1
#define DATA_PACKET_LENGTH (BIT_8_DATA_PACKET_LENGTH<<8)
//SWD MODE
#define SWD PIN LOW (0x0<<6)
#define SWD_PIN_HIGH_AFTER_NEXT_SYNCWORD (0x1<<6)
#define SWD_HIGH_AFTER_NEXT_SYNCWORD_INTERRUPT_PIN_HIGH (0x2<<6)
#define INTERRUPT_PIN_HIGH (0x3<<6)
//LOCK THRESHOLD MODE
#define THRESHOLD_FREE_RUNNING (0x0<<4)
#define LOCK_THRESHOLD_AFTER_NEXT_SYNCWORD (0x1<<4)
#define LOCK_THRESHOLD_AFTER_NEXT_SYNCWORD_FOR_DATA_PACKET (0x2<<4)
#define LOCK_THRESHOLD (0x3<<4)
/***********************************************************************************/
/********* define FSK_3_4FSK_DEMOD_REGISTER_13 ********************/
#define BIT_4_FSK3_PREAMBLE_TIME_VALIDATE 0
#define BIT_7_FSK3_CDR_THRESHOLD 0
#define BIT_7_FSK3_FSK4_SLICER_THRESHOLD 0
#define FSK3_PREAMBLE_TIME_VALIDATE (BIT_4_FSK3_PREAMBLE_TIME_VALIDATE<<22)
#define FSK3_CDR_THRESHOLD (BIT_7_FSK3_CDR_THRESHOLD<<15)
//VITERBI_PATH_MEMORY
#define BITS_4_VITERBI_PATH_MEMORY (0x0<<13)
#define BITS_6_VITERBI_PATH_MEMORY (0x1<<13)
#define BITS_8_VITERBI_PATH_MEMORY (0x2<<13)
#define BITS_32_VITERBI_PATH_MEMORY (0x3<<13)
#define PHASE_CORRECTION (0x1<<12)
#define FSK3_VITERBI_DETECTOR (0x1<<11)
#define FSK3_FSK4_SLICER_THRESHOLD (BIT_7_FSK3_FSK4_SLICER_THRESHOLD<<4)
/***********************************************************************************/
/********* define TEST_DAC_REGISTER_14 ********************/
#define BIT_3_ED_LEAK_FACTOR 0
#define BIT_4_TEST_DAC_GAIN 0
#define BIT_16_TEST_DAC_OFFSET 0
#define NO_PULSE_EXTENSION (0x0<<30)
#define EXTENDED_BY_1 (0x1<<30)
#define EXTENDED_BY_2 (0x2<<30)
#define EXTENDED_BY_3 (0x3<<30)
#define ED_LEAK_FACTOR (BIT_3_ED_LEAK_FACTOR<<27)
//PULSE_EXTENSION
#define FULL_RESPONSE_TO_PEAK (0x0<<25)
#define RESPONSE_0_5_TO_PEAK (0x1<<25)
#define RESPONSE_0_25_TO_PEAK (0x2<<25)
#define RESPONSE_0_125_TO_PEAK (0x3<<25)
#define TEST_DAC_GAIN (BIT_4_TEST_DAC_GAIN<<21)
#define TEST_DAC_OFFSET (BIT_16_TEST_DAC_OFFSET<<5)
#define TEST_TDAC_EN (0x1<<4)
/***********************************************************************************/
/********* define TEST_MODE_REGISTER_15 ********************/
//CAL OVERRIDE
#define AUTO_CAL (0x0<<30)
#define OVERRIDE_GAIN (0x1<<30)
#define OVERRIDE_BW (0x2<<30)
#define OVERRIDE_BW_AND_GAIN (0x3<<30)
#define REG_1_PD (0x1<<29)
#define FORCE_LD_HIGH_8 (0x1<<28)
//ANALOG_TEST_MODES
#define BAND_GAP_VOLTGE (0x0<<24)
#define CURRENT_40uA_FROM_REG4 (0x1<<24)
#define FILTER_I_CHANNEL_STAGE_1 (0x2<<24)
#define FILTER_I_CHANNEL_STAGE_2 (0x3<<24)
#define FILTE_I_CHANNEL_STAGE_1 (0x4<<24)
#define FILTER_Q_CHANNEL_STAGE_1 (0x5<<24)
#define FILTER_Q_CHANNEL_STAGE_2 (0x6<<24)
#define FILTE_Q_CHANNEL_STAGE_1 (0x7<<24)
#define ADC_REFERENCE_VOLTAGE (0x8<<24)
#define BIAS_CURRENT_FROM_RSSI_5uA (0x9<<24)
#define FILTER_COARSE_CAL_OSCILLATOR_O_P (0xa<<24)
#define ANALOG_RSSI_I_CHANNEL (0xb<<24)
#define OSET_LOOP_VE_FBACK_V_I_CH (0xc<<24)
#define SUMMED_O_P_OF_RSSI_RECTIFIER_P (0xd<<24)
#define SUMMED_O_P_OF_RSSI_RECTIFIER_N (0xe<<24)
#define BIAS_CURRENT_FROM_BB_FILTER (0xf<<24)
//PLL_TEST_MODES
#define NORMAL_OPERATION (0x0<<20)
#define RDIV (0x1<<20)
#define NDIV (0x2<<20)
#define RCNTR_2_ON_MUXOUT (0x3<<20)
#define NCNTR_2_ON_MUXOUT (0x4<<20)
#define ACNTR_TO_MUXOUT (0x5<<20)
#define PFD_PUMP_UP_TO_MUXOUT (0x6<<20)
#define PFD_PUMP_DN_TO_MUXOUT (0x7<<20)
#define SDATA_TO_MUXOUT_OR_SREAD (0x8<<20)
#define ANALOG_LOCK_DETECT_ON_MUXOUT (0x9<<20)
#define END_OF_COARSE_CAL_ON_MUXOUT (0xa<<20)
#define END_OF_FINE_CAL_ON_MUXOUT (0xb<<20)
#define FORCE_NEW_PRESCALER_CONFIG_FOR_ALL_N (0xc<<20)
#define TEST_MUX_SELECTS_DATA (0xd<<20)
#define LOCK_DETECT_PERCISION (0xe<<20)
//#define RESERVED (0xf<<20)
//CLK_-MUX
#define NORMAL_NO_OUTPUT (0x0<<17)
#define DEMOD_CLK (0x1<<17)
#define CDR_CLK (0x2<<17)
#define SEQ_CLK (0x3<<17)
#define BB_OFFSET_CLK (0x4<<17)
#define SIGMA_DELTA_CLK (0x5<<17)
#define ADC_CLK (0x6<<17)
#define TxRxCLK (0x7<<17)
//PFD/CP_TEST_MODES
#define DEFAULT_NO_BLEED (0x0<<14)
#define VE_CONSTANT_BLEED (0x1<<14)
#define CVE_CONSTANT_BLEED (0x2<<14)
#define CVE_PULSED_BLEED (0x3<<14)
#define CVE_PULSE_BLD_DELAY_UP (0x4<<14)
#define CPPUMPUP (0x5<<14)
#define CPTRI_STATE (0x6<<14)
#define CPPUMPDN (0x7<<14)
//¦²-¦¤_TEST_MODES
#define DEFAULT_3RD_ORDER_SD_NO_DITHER (0x0<<11)
#define ST1_ORDER_SD (0x1<<11)
#define ND2_ORDER_SD (0x2<<11)
#define DITHER_TO_FIRST_STAGE (0x3<<11)
#define DITHER_TO_SECOND_STAGE (0x4<<11)
#define DITHER_TO_THIRD_STAGE (0x5<<11)
#define DITHER_8 (0x6<<11)
#define DITHER_32 (0x7<<11)
//Tx_TEST_MODES
#define Tx_CARRIER_ONLY (0x0<<8)
#define Tx_PVE_TONE_ONLY (0x1<<8)
#define Tx_NVE_TONE_ONLY (0x2<<8)
#define Tx_1010_PATTERN (0x3<<8)
#define Tx_PN9_DATA_AT_PROGRAMED_RATE (0x4<<8)
#define Tx_SYNC_BYTE_REPEATEDLY (0x5<<8)
#define NORMAL_OPERAT (0x6<<8)
//Rx_TEST_MODES
#define Rx_TEST_MODES_NORMAL (0x0<<4)
#define SCLK_SDATA_I_Q (0x1<<4)
#define REVERSE_I_Q (0x2<<4)
#define LINEAR_SLICER_ON_RXDATA (0x3<<4)
#define CORRELATOR_SLICER_ON_TxRxDATA (0x4<<4)
#define ADDITIONAL_FILTERING_ON_I_Q (0x5<<4)
#define ENVELOPE_DETECTOR_WATCHDOG_DISABLED (0x6<<4)
//#define RESERVED (0x7<<4)
#define ENABLE_REG_14_DEMOD_PARAMETERS (0x8<<4)
#define PROHIBIT_CALACTIVE (0x9<<4)
#define ENABLE_DEMOD_DURING_CAL (0xa<<4)
#define FORCE_CALACTIVE (0xb<<4)
#define I_Q_TO_TxRxCLK_TxRxDATA (0xc<<4)
#define POWER_DOWN_DDT_AND_ED_IN_T_4_MODE (0xd<<4)
#define SDATA_TO_CDR (0xe<<4)
#define FSK3_SLICER_ON_TxRxDATA (0xf<<4)
unsigned long int ADF7021Registers[16];
void init_adf();
void ADF7021Registers_TRANSMITTER_config(void);
void ADF7021Registers_RECEIVER_config(void);
void init_adf()
{
int1 i;
output_low( ADF_DI);
output_low( ADF_CLK);
output_low( ADF_SELECT);
i=input(ADF_DO);
setup_spi(SPI_MASTER | SPI_H_TO_L | SPI_CLK_DIV_16);
output_high(ADF_SELECT);
}
void ADF7021Registers_TRANSMITTER_config (void)
{
ADF7021Registers[0]=N_REGISTER_0|TRANSMIT|INTEGER_N|FRACTIONAL_N_Tx;
ADF7021Registers[1]=VCO_OSCILLATOR_REGISTER_1|XOSC_ENABLE|R_COUNTER_DIVIDE_RATIO|XTAL_BIAS|CP_CURRENT|VCO_LOOP_CONDITION_ON|VCO_BIASCURRENT;
ADF7021Registers[2]=TRANSMIT_MODULATION_REGISTER_2|PA_ENABLE|PA_BIAS|POWER_AMPLIFIER|Tx_FREQUENCY_DEVIATION|FSK_2|TxINVERT_NORMAL;
ADF7021Registers[3]=TRANSMIT_RECEIVE_CLOCK_REGISTER_3|AGC_CLK_DIVIDE|SEQUENCER_CLK_DIVIDE|CDR_CLK_DIVIDE|DEM_CLK_DIVIDE|BBOS_CLK_DIVIDE;
ADF7021Registers[4]=DEMODULATOR_SETUP_REGISTER_4|IF_BW_25kHz|POST_DEMOD_BW|DISCRIMINATOR_BW|Rx_INVERT_NORMAL|DEMOD_SCHEME_2FSK_CORRELATOR;
ADF7021Registers[5]=IF_FILTER_SETUP_REGISTER_5|IF_CAL_COARSE|IF_FILTER_DIVIDER|IF_FILTER_ADJUST|IR_PHASE_ADJUST_MAG|IR_GAIN_ADJUST_MAG;
ADF7021Registers[6]=IF_FINE_CAL_SETUP_REGISTER_6|IF_CAL_LOWER_TONE_DIVIDE|IF_CAL_UPPER_TONE_DIVIDE|IF_CAL_DWELL_TIME|IR_CAL_SOURCEDRIVE_LEVEL_OFF;
ADF7021Registers[7]=READBACK_SETUP_REGISTER_7;
ADF7021Registers[8]=POWER_DOWN_TEST_REGISTER_8;
ADF7021Registers[9]=AGC_REGISTER_9|AGC_LOW_THRESHOLD|AGC_HIGH_THRESHOLD|AUTO_AGC|LNA_GAIN_3|FILTER_GAIN_8|LNA_CURRENT;
ADF7021Registers[10]=AFC_REGISTER_10|AFC_SCALING_FACTOR|KI|KP|MAX_AFC_RANGE;
ADF7021Registers[11]=SYNC_WORD_DETECT_REGISTER_11|SYNC_24_BITS|SYNC_BYTE_SEQUENCE|ACCEPT_0_ERRORS;
ADF7021Registers[12]=SWD_THRESHOLD_SETUP_REGISTER_12|THRESHOLD_FREE_RUNNING|SWD_HIGH_AFTER_NEXT_SYNCWORD_INTERRUPT_PIN_HIGH|DATA_PACKET_LENGTH;
ADF7021Registers[13]=FSK_3_4FSK_DEMOD_REGISTER_13;
ADF7021Registers[14]=TEST_DAC_REGISTER_14;
ADF7021Registers[15]=TEST_MODE_REGISTER_15;
}
void ADF7021Registers_RECEIVER_config (void)
{
ADF7021Registers[0]=N_REGISTER_0|RECEIVE|INTEGER_N|FRACTIONAL_N_Rx;
ADF7021Registers[1]=VCO_OSCILLATOR_REGISTER_1|XOSC_ENABLE|R_COUNTER_DIVIDE_RATIO|XTAL_BIAS|CP_CURRENT|VCO_LOOP_CONDITION_ON|VCO_BIASCURRENT;
ADF7021Registers[2]=TRANSMIT_MODULATION_REGISTER_2|PA_ENABLE|PA_BIAS|POWER_AMPLIFIER|Tx_FREQUENCY_DEVIATION|FSK_2|TxINVERT_NORMAL;
ADF7021Registers[3]=TRANSMIT_RECEIVE_CLOCK_REGISTER_3|AGC_CLK_DIVIDE|SEQUENCER_CLK_DIVIDE|CDR_CLK_DIVIDE|DEM_CLK_DIVIDE|BBOS_CLK_DIVIDE;
ADF7021Registers[4]=DEMODULATOR_SETUP_REGISTER_4|IF_BW_25kHz|POST_DEMOD_BW|DISCRIMINATOR_BW|Rx_INVERT_NORMAL|DEMOD_SCHEME_2FSK_CORRELATOR;
ADF7021Registers[5]=IF_FILTER_SETUP_REGISTER_5|IF_CAL_COARSE|IF_FILTER_DIVIDER|IF_FILTER_ADJUST|IR_PHASE_ADJUST_MAG|IR_GAIN_ADJUST_MAG;
ADF7021Registers[6]=IF_FINE_CAL_SETUP_REGISTER_6|IF_CAL_LOWER_TONE_DIVIDE|IF_CAL_UPPER_TONE_DIVIDE|IF_CAL_DWELL_TIME|IR_CAL_SOURCEDRIVE_LEVEL_OFF;
ADF7021Registers[7]=READBACK_SETUP_REGISTER_7;
ADF7021Registers[8]=POWER_DOWN_TEST_REGISTER_8;
ADF7021Registers[9]=AGC_REGISTER_9|AGC_LOW_THRESHOLD|AGC_HIGH_THRESHOLD|AUTO_AGC|LNA_GAIN_3|FILTER_GAIN_8|LNA_CURRENT;
ADF7021Registers[10]=AFC_REGISTER_10|AFC_SCALING_FACTOR|KI|KP|MAX_AFC_RANGE;
ADF7021Registers[11]=SYNC_WORD_DETECT_REGISTER_11|SYNC_24_BITS|SYNC_BYTE_SEQUENCE|ACCEPT_0_ERRORS;
ADF7021Registers[12]=SWD_THRESHOLD_SETUP_REGISTER_12|THRESHOLD_FREE_RUNNING|SWD_HIGH_AFTER_NEXT_SYNCWORD_INTERRUPT_PIN_HIGH|DATA_PACKET_LENGTH;
ADF7021Registers[13]=FSK_3_4FSK_DEMOD_REGISTER_13;
ADF7021Registers[14]=TEST_DAC_REGISTER_14;
ADF7021Registers[15]=TEST_MODE_REGISTER_15;
} |
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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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| Posted: Mon Mar 09, 2015 11:02 am |
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| Code: |
#define ACCEPT_0_ERRORS (0x0<<6)
#define IF_BW_12_5kHz (0x0<<30)
#define Rx_INVERT_NORMAL (0x0<<8)
.....
#define SWD PIN LOW (0x0<<6)
above as two problems for the coding of one
.........
#define ADF_SELECT PIN_C0 //C1
#define ADF_CLK PIN_C3
#define ADF_DI PIN_C2 //mosi
#define ADF_DO PIN_C4 //miso
output_low( ADF_DI);
output_low( ADF_CLK);
output_low( ADF_SELECT);
i=input(ADF_DO);
setup_spi(SPI_MASTER | SPI_H_TO_L | SPI_CLK_DIV_16);
|
you have lots of assorted trouble here - but you are calling for a HARDWARE SPI setup in your code .
recall that on 18F PICS SDO is pin_C5 while SDI i PIN_C4
i especially fond of expressions in the form of 0x0<< anything
and
also placing ANY text on a #define line - before a <CR> can be problematic
as the compiler directive is a text replace command.
SEE:
#define ADF_SELECT PIN_C0 //C1
#define SWD PIN LOW (0x0<<6)
overall, you have posted a very odd attempt at creating constants in your defines, and i am not at all sure they will compile to what you desire.
you clearly have a very long way to go before you are even ready to attempt actually configuring the part.
Having a working SPI command channel is your immediate challenge...
followed closely by the need to be well versed in the RF hardware aspects of what you want to achieve -circuit wise.
all the code in the world won't fix a lack of understanding of the RF functions of the chip you wish to use. this is a very flexible part with many similar uses- but not at all "plug and play".. |
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prasad_21
Joined: 12 Nov 2014
Posts: 11
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| Posted: Wed Mar 11, 2015 3:34 am |
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@asmboy
Thanks for viewing my code.
I am calling Hardware SPI as i am using hardware SPI circuit wise and the channel is working. The expressions in the form of (0x0<<) are used for the register bits configuration, as far as #define SWD PIN LOW (0x0<<6) is concerned, this is done for selection of the SWD mode in Register 12 of ADF7021. I already have a proven hardware all i have to do is a firmware for which i am doing the driver programming. |
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temtronic
Joined: 01 Jul 2010
Posts: 9161
Location: Greensville,Ontario
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| Posted: Wed Mar 11, 2015 5:23 am |
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I have to agree with asmboy about the defines. It is not the 'normal' or 'regular' way to assign bits to a register. Every datasheet for every micro or peripheral I've ever read shows the 'registers' as a group of bits so the feature is represented as a binary pattern (IE: 0b00110101) as opposed to a hex value left shifted a decimal value.
If you'd used the datasheet format then everyone can quickly compare and see if you've miscomputed a define. As you've done it , I can't see if they're right or wrong. Obviously ,if you have ONE define wrong the driver will not function correctly. That one error could take you days to discover.
I have to assume you have a pair of premade modules and not raw chips. If so a basic drive should be easy as I also assume there's a 'default' or 'test' configuration for the ADF7021 device. If you have a premade module, post a link to the device,there may be a driver 'on the web' already.
Jay |
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asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
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| Posted: Wed Mar 11, 2015 1:31 pm |
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| Code: |
#define SWD PIN LOW (0x0<<6)
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how do you USE this define in your program code ?
normally i would expect the form SWD_PIN_LOW
but with the extra spaces you have in the #define
I am wondering how you use this text substitution w/o the compiler
halting and barfing an error at you.....  |
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ckielstra
Joined: 18 Mar 2004
Posts: 3680
Location: The Netherlands
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| Posted: Wed Mar 11, 2015 4:07 pm |
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| Code: | #define ADF_SELECT PIN_C0 //C1
#define ADF_CLK PIN_C3
#define ADF_DI PIN_C2 //mosi
#define ADF_DO PIN_C4 //miso
output_low( ADF_DI);
output_low( ADF_CLK);
output_low( ADF_SELECT);
i=input(ADF_DO);
setup_spi(SPI_MASTER | SPI_H_TO_L | SPI_CLK_DIV_16); |
This part confuses me.
| prasad_21 wrote: | | I am calling Hardware SPI as i am using hardware SPI circuit wise and the channel is working. |
You say you are using hardware SPI, but on you PIC18LF14K22 the SDO is on PIN_C7 and SDI on PIN_B4. You are using C2, respectively C4.
Also, the ADF7021 is generating the clock, so that chip should be the SPI master.
Your SPI setup configures for SPI mode 2, that's wrong. I can't easily find the right SPI mode for this chip, but at least it is clear the data is clocked in at the rising clock edge. This means you have to use SPI mode 0 or 3, my guess would be it is a mode 0 setup.
I always use the following conversion table to configure the SPI settings: | Code: | // SPI Mode | MOTOROLA | MICROCHIP | CCS | Clock line idle | Data clocked in at
//----------------------------------------------------------------|-----------------|-------------------
// | CPOL CPHA| CKP CKE | | |
// 0 | 0 0 | 0 1 | SPI_L_TO_H | SPI_XMIT_L_TO_H | low | low to high edge
// 1 | 0 1 | 0 0 | SPI_L_TO_H | low | high to low edge
// 2 | 1 0 | 1 1 | SPI_H_TO_L | high | high to low edge
// 3 | 1 1 | 1 0 | SPI_H_TO_L | SPI_XMIT_L_TO_H | high | low to high edge
//
// Example: setup_spi(SPI_MASTER | SPI_MODE_3 | SPI_CLK_DIV_4 );
#define SPI_MODE_0 (SPI_L_TO_H | SPI_XMIT_L_TO_H)
#define SPI_MODE_1 (SPI_L_TO_H)
#define SPI_MODE_2 (SPI_H_TO_L)
#define SPI_MODE_3 (SPI_H_TO_L | SPI_XMIT_L_TO_H) |
Last but not least, where is your SPI configuration for the ADF7021? This requires setting R0_DB28 to 1 and setting R15_DB[17:19] to 0x7. Both these settings are missing from your program. |
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temtronic
Joined: 01 Jul 2010
Posts: 9161
Location: Greensville,Ontario
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| Posted: Wed Mar 11, 2015 4:41 pm |
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tidbits I've found..
chip is $4
eval board is $75
complete C code ( for another micro) is on the web.....
at least one other has been to this forum about the chip...
Jay |
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prasad_21
Joined: 12 Nov 2014
Posts: 11
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| Posted: Wed Mar 11, 2015 11:30 pm |
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@temtronic
I have taken help of the driver available for another micro which is the supporting document for the evaluation board and written this code. The module which i have is a custom built module and no link can be provided for it to search for a driver directly on web, i have tried all of it. |
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