 |
 |
| View previous topic :: View next topic |
| Author |
Message |
sresam89
Joined: 15 Mar 2012
Posts: 20
Location: India
|
| 16f877a SPI slave read problem |
 Posted: Mon Sep 10, 2012 11:15 pm |
 |
|
hi all
I am trying to implement spi communication between two 16f877a.
I am giving my CCS (4.038) code below:
For master
| Code: |
void main()
{
TRISC=0x10; //SCK is output (Master), SDI is input,
TRISA=0x00; //Slave Select Bit
ADCON1=0x06;
SSPSTAT=0x40; //Mode 1,1 SPI, middle of output time sampling
SSPCON=0x31; //Mode 1,1 SPI Master, 1/16 Tosc bit, SSP is on
SSPIF=0;
WCOL=0;
SSPBUF=0;
lcd_init();
do{
i=0;
ss=0; //also tried always tying Slave SS pin to gnd instead of switching
lcd_putc("\fDATA TRANSMIT\n");delay_ms(2000);
while(wcol);
SSPBUF='b';
while(!SSPIF);
SSPIF=0;
ss=1; //also tried always tying Slave SS pin to gnd instead of switching
printf(lcd_putc,"\fDATA done:1 %C",SSPBUF); delay_ms(3000);
ss=0; //also tried always tying Slave SS pin to gnd instead of switching
lcd_putc("\fDATA TRANSMIT\n");delay_ms(2000);
while(wcol);
SSPBUF='a';
while(!SSPIF);
SSPIF=0;
ss=1; //also tried always tying Slave SS pin to gnd instead of switching
lcd_putc("\fDATA done:2"); delay_ms(3000);
}while(1);
}
|
The code is fine and is transmitting perfectly. I checked using proteus. I also verified using some hard way (mentioned later).
For slave
| Code: |
void main()
{
int8 i=0;
TRISC=0x18;//SCK is input (Slave), SDI is input,SDO is output, all others output
TRISA=0X10;//SLAVE Select Bit
ADCON1=0x06;
SSPSTAT=0x40;//Mode 1,1 SPI, middle of output time sampling
SSPCON=0x34;//SPI Slave Mode(SS bit controlled), 1/16 Tosc bit, SSP is on
SSPBUF=0;
SSPIF=0;
lcd_init();
while(1){
lcd_putc("\fwaiting");
while((BF==0));
SSPIF=0;
printf(lcd_putc," :%c",SSPBUF);
lcd_putc("\ndata");DELAY_MS(500);
}
}
|
This receiver is receiving initially (soon after reset at any point of time) a single character only and halts indefinitely at "waiting" for SSPIF (also tried switching it to BF). The transmitter is sending all the characters mentioned in the program (verified using reset @ slave Before every Tx from Master).
Last edited by sresam89 on Wed Sep 12, 2012 4:39 am; edited 1 time in total |
|
 |
sresam89
Joined: 15 Mar 2012
Posts: 20
Location: India
|
|
| Posted: Tue Sep 11, 2012 3:37 am |
|
|
| solved it by changing the SSPCON VALUE to 0x35 |
|
|
sresam89
Joined: 15 Mar 2012
Posts: 20
Location: India
|
|
| Posted: Wed Sep 12, 2012 4:40 am |
|
|
| sresam89 wrote: | | solved it by changing the SSPCON VALUE to 0x35 |
hello all.
i have a small query...
i know writing 0x35 to SSPCON ll control the salve using SlaveSelect pin @ PA.5, also the salve pin need to be controlled by the master by pulling it to ground to select the slave. All good till now..
the query is..
1.is it so that the SS pin be toggled after/before every 8-bit Data reception? (i found it working only so). permanent grounding dint work.
2.connecting the SS pin of slave(PA.5) directly to any port-pin of master to select it also din work out. either i need to use a transistor to switch it or do it manually!. Why was this happening.
though i have not put the code for my query i hope someone could help, with one posted. |
|
|
RF_Developer
Joined: 07 Feb 2011
Posts: 839
|
|
| Posted: Wed Sep 12, 2012 5:05 am |
|
|
CCS C has built in routines supporting SPI. You don't normally need to set any registers directly in CCS C. You have written assembler or other C (e.g. Hitech) style code, not CCS style code.
From the datasheet I see that setting the SSPCON to 0x05 in 0x35 forces the SPI to ignore the SS pin entirely: this is not likely to be the best way to get this to work.
Many SPI slaves require slave select (SS or CS or whatever name - it is not standardised) to stay active for the whole sequence of bytes. They use it internally to synchronise their interpretation of the data. Many assume that if the select goes inactive it means the master has aborted the transaction and that anything the slave has doen so far should be ignored. So SS should be set active before the first byte of the sequence. The slave then knows the first byte received after SS goes active IS the first byte of a transaction sequence, and kept there until the sequence has been completed or is aborted, e.g. due to master reset.
SS is required in where there is more than one slave, and whenever there is any possibility that the master and slave cen get out of sync for any reason, which in practice means in most SPI situations.
Summary:
Master:
Set SS for the required slave active.
Send and receive all required bytes.
Clear/deactivate SS.
Slave:
Ignore anything until SS goes active.
Buffer all data but don't do anything with it until SS clears.
If SS clears before transaction (i.e. all bytes, send and receive as needed) complete, then clear the buffer.
Only do something, e.g. write to flash memory, change PWM parameters, sample analogue signals and so on, if transaction was completed correctly.
RF Developer |
|
|
|
|
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum
|
Powered by phpBB © 2001, 2005 phpBB Group
|
FAQ 
Search
Register
Profile 
Log in to check your private messages 
Log in
