![](templates/subSilver/images/CCSLogo.jpg) |
![CCS C Software and Maintenance Offers](templates/subSilver/images/forumAd6.jpg) |
View previous topic :: View next topic |
Author |
Message |
peterpanic
Joined: 05 Apr 2010 Posts: 17 Location: UK
|
18F47J13 clock configuration |
Posted: Tue Mar 20, 2012 11:05 am |
|
|
The 47J13 has a very competent (i.e. complex) clock configuration, and I want to use the internal oscillator at 8MHz to drive the 96MHz PLL. It is far from clear what the "magic spells" are.
I currently have (set by the project wizard)
Code: |
#fuses PLL2
#fuses PLL96MHZ
#use delay( int=48000000, restart_wdt)
setup_oscillator(OSC_8MHZ | OSC_INTRC | OSC_31250 | OSC_PLL_OFF); |
and the compiler complains about the use_delay line with error 99 "option invalid internal osc freq wrong"
Can anyone help, please? _________________ - peter - |
|
![](templates/subSilver/images/spacer.gif) |
PCM programmer
Joined: 06 Sep 2003 Posts: 21708
|
|
Posted: Tue Mar 20, 2012 4:50 pm |
|
|
I don't have this PIC to test, but try this LED blinking program and
see if it works:
Code: |
#include <18F47J53.h>
#fuses INTRC_PLL_IO, PLL2, PLLEN, NOWDT
#use delay(clock=48M)
//======================================
void main(void)
{
// Blink LED at 1 Hz rate.
while(1)
{
output_toggle(PIN_B0);
delay_ms(500);
}
} |
|
|
![](templates/subSilver/images/spacer.gif) |
peterpanic
Joined: 05 Apr 2010 Posts: 17 Location: UK
|
|
Posted: Wed Mar 21, 2012 2:06 pm |
|
|
> try this LED blinking program and see if it works:
works fine, except the actual delay period measures 1500ms, not 500. But at least the compiler doesn't barf. Working on it, and will report... _________________ - peter - |
|
![](templates/subSilver/images/spacer.gif) |
peterpanic
Joined: 05 Apr 2010 Posts: 17 Location: UK
|
|
Posted: Wed Mar 21, 2012 5:41 pm |
|
|
Looks to me like two compiler bugs; the first is that the compiler doesn't "understand" the 96MHz PLL, and the second is that when using the ICD U-64, the config words get mangled - as well as changing the DEBUG and STVREN bits it also changes PLLSEL and WTDPS1 bits. Reported (not via the IDE reporting system which seems to be broken for me). _________________ - peter - |
|
![](templates/subSilver/images/spacer.gif) |
dyeatman
Joined: 06 Sep 2003 Posts: 1924 Location: Norman, OK
|
|
Posted: Wed Mar 21, 2012 6:28 pm |
|
|
Where did you get the info that the PLL went to 96MHZ? From page
11 of the data sheet:
Quote: | A Phase Lock Loop (PLL) frequency multiplier
available to the high-speed crystal, and external
and internal oscillators, providing a clock speed
up to 48 MHz.
|
_________________ Google and Forum Search are some of your best tools!!!! |
|
![](templates/subSilver/images/spacer.gif) |
peterpanic
Joined: 05 Apr 2010 Posts: 17 Location: UK
|
|
Posted: Thu Mar 22, 2012 2:31 am |
|
|
PLL runs at 96MHz, its output is divided by two to provide the 48MHz (max) processor clock.
p35 of data sheet: "The PIC18F47J13 provides two PLL circuits: a 4x multiplier PLL and a 96 MHz PLL enabling 48 MHz operation from the 8 MHz
internal oscillator." _________________ - peter - |
|
![](templates/subSilver/images/spacer.gif) |
Ttelmah
Joined: 11 Mar 2010 Posts: 19359
|
|
Posted: Thu Mar 22, 2012 4:57 am |
|
|
I always start by working out what bits have to be set where to do what I want.
So, working through the clock diagram from fig 3-1, we need FOSC:2=0 to say feed the internal oscillator to the PLL. Then PLLSEL set to 0. Then PLLDIV set to 110, and either PLLEN, or CFGPLLEN set to 1. FOSC 2:0 = something other than 00. OSCCON 1:0 = 00.
So then look where these come from. CFGPLLEN, PLLDIV, PLLSEL, & FOSC, are all in the fuses, while OSCCON is a user setting.
Then step into the device editor, and look at what CCS setting sets these bits. This is the little window in the top right of device editor, which shows CCS fuse 'names', and what registers/bits are masked and set for each of these. So, need to get : xxx1110x in the first register and xxxxx01x in the second. PLL2, correctly gives the low nibble for the first, and PLLEN, the high nibble. Then INTRC_PLL, or INT_RC_PLL_IO look to give the required bits in the second byte. PLLSEL requires bit 2 of byte 5, and this is set by the PLL fuse.
So we should need:
PLL, INTRC_PLL_IO, PLL2
Then 'be careful' CCS has become increasingly complex regarding the 'clock' setting. If you say 'crystal', 'internal', or other similar keywords, it overrides individual fuses to setup what it 'thinks' is right. Safer, to just use the 'clock' keyword, which appears to always leave your fuses as they are. This may be the 'core' problem.
So, now all that is needed is the OSCCON bits. Two choices 'setup_oscillator', or go 'DIY'. Looking at the setup_oscillator settings, 'OSC_NORMAL' is '00' for the required bits. This should be the 'default', but select it anyway.
So then trying:
Code: |
#include <18F47J13.h>
#device adc=16
#FUSES NOWDT //No Watch Dog Timer
#FUSES PLL2 //Divide By 2(8MHz oscillator input)
#FUSES PLLEN
#FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES INTRC_PLL_IO
#FUSES NOCLOCKOUT
#FUSES NOFCMEN //Fail-safe clock monitor disabled
#FUSES NOIESO //Internal External Switch Over mode disabled
#use delay(clock=48000000)
void main()
{
setup_oscillator(OSC_NORMAL);
setup_comparator(NC_NC_NC_NC);
do {
output_toggle(PIN_A0);
} while (TRUE);
}
|
Seems to have every fuse and register that needs to be setup for the 48MHz operation, set 'right'. Haven't got a chip of this type to try, but in the debugger, everything does appear 'right'.
Best Wishes |
|
![](templates/subSilver/images/spacer.gif) |
peterpanic
Joined: 05 Apr 2010 Posts: 17 Location: UK
|
|
Posted: Thu Mar 22, 2012 7:01 am |
|
|
Quote: | Then step into the device editor, and look at what CCS setting sets these bits. This is the little window in the top right of device editor, which shows CCS fuse 'names', and what registers/bits are masked and set for each of these. |
Thanks - that was one of the missing links for me.
Tried the code and... it runs at 31kHz! (I changed NOCLOCKOUT to CLOCKOUT and INTRC_PLL_IO to INTRC_PLL and measured the period on the CLKOUT pin - 7.83kHz) _________________ - peter - |
|
![](templates/subSilver/images/spacer.gif) |
Ttelmah
Joined: 11 Mar 2010 Posts: 19359
|
|
Posted: Thu Mar 22, 2012 9:50 am |
|
|
OK.
The accuracy of this, suggests it is from the 8MHz source divided down, rather than from the separate INTRC source.
So only routes are:
OSCTUNE 7 = 1 (fair enough we are not changing this, might well be 1).
OSCCON 6:4 = 000 (OK, we set this whole register to 0).
Then _either_ OSCCON 1:0 = 11, or FOSC 2:1 = 00, to give 31KHz out.
Now, for me, OSCCON 1:0, is set to 00, and the fuses have FOSC 2:1 set to 10
What do these show for your, if you load the code into a simulator like MPLAB?.
What compiler version are you using?.
Best Wishes |
|
![](templates/subSilver/images/spacer.gif) |
peterpanic
Joined: 05 Apr 2010 Posts: 17 Location: UK
|
|
Posted: Thu Mar 22, 2012 5:52 pm |
|
|
Quote: | Now, for me, OSCCON 1:0, is set to 00, and the fuses have FOSC 2:1 set to 10 |
FOSC should be 01 (so that the 96M prescaler sees internal rather than external). That's what the hex file loads.
Quote: | What compiler version are you using?. |
4.130
I note that there's an error in the CCS header file - if defines OSC_INTRC as 2 which is reserved - should be 3.
Sorry, but I have run out of time - I'm going to use it at 32MHz and sort this out when the job is done (should have been several days ago). Thanks for listening... _________________ - peter - |
|
![](templates/subSilver/images/spacer.gif) |
peterpanic
Joined: 05 Apr 2010 Posts: 17 Location: UK
|
|
Posted: Thu Mar 22, 2012 6:09 pm |
|
|
I also see there is a Mchip silicon errata item which explains that, even though it's not used, you have to set the INTOSC prescaler selector to 4MHz or 8MHz. _________________ - peter - |
|
![](templates/subSilver/images/spacer.gif) |
|
|
You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum
|
Powered by phpBB © 2001, 2005 phpBB Group
|