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kongfu1
Joined: 26 Apr 2010
Posts: 56
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| SPI is not working with PCD v4.117 |
 Posted: Fri Jan 14, 2011 9:44 pm |
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Hi,
I am using PCD v4.117 and PIC24FJ256GB206. SPI device is a flash memory m25p128. There are two m25p128 connected together with different chip select IO from PIC. With old PCD 3.249, everything is working (18f452 to control spi) device).
m25p128 shall take 3-5 seconds to erase 16MB memory. During that time status register shall be 255. After erasing, the register should be 0.
With scope, clock and data in are perfect. But data from spi_read is 0 all the time.
Attached is my code. Please help.
Thanks.
Howard
| Code: |
#include <24FJ256GB206.h>
#fuses NOPR,HS,PROTECT,NOWDT
#use delay(clock=32M, crystal)
#zero_ram
//FRONT PANNEL
#define FP_RX PIN_F4 //INTPUT
#define FP_TX PIN_F5 //OUTPUT
#pin_select U1RX=FP_RX
#pin_select U1TX=FP_TX
#use rs232(UART1,baud=115200,bits=8, parity=N, stop=1, errors, stream=FP,restart_wdt)
//SPI pin
#define SPI_DATA_OUT PIN_G7 //OUTPUT
#define SPI_DATA_IN PIN_G8 //INPUT
#define SPI_CLK PIN_G6 //INPUT
#define SPI_MEM_HOLD PIN_E5 //OUTPUT - 0 IS ON HOLD
#define SPI_MEM_CS1 PIN_E6 //OUTPUT
#define SPI_MEM_CS2 PIN_G9 //OUTPUT
//SPI map
#pin_select SCK1OUT=SPI_CLK
#pin_select SDO1=SPI_DATA_OUT
#pin_select SS1OUT=SPI_DATA_IN
#define WREN_CMD 0x06 //Write Enable
#define WRDI_CMD 0x04 //Write Disable
#define RDSR_CMD 0x05 //Read Status Register
#define WRSR_CMD 0x01 //Write Status Register
#define READ_CMD 0x03 //Read Data Bytes
#define FAST_READ_CMD 0x0b //Read Data Bytes at Higher Speed
#define PP_WRITE_CMD 0x02 //Page Program
#define SEC_ERASE_CMD 0xd8 //Sector Erase
#define ALL_ERASE_CMD 0xc7 //Bulk Erase
#define RDID_CMD 0xb9 //Read Identification
void main()
{
unsigned int8 i, data = 1;
output_high(SPI_MEM_CS1); // Start CS high
output_high(SPI_MEM_CS2); // Start CS high
output_low(SPI_MEM_HOLD);
output_high(SPI_CLK); // Start CLK high
// setup SPI with master and rising edge transmit
setup_spi(SPI_MASTER | SPI_L_TO_H | SPI_XMIT_L_TO_H | SPI_CLK_DIV_16);
enable_interrupts(INT_RDA);
enable_interrupts(INTR_GLOBAL);
output_high(SPI_MEM_HOLD); //enable flash memory chip
delay_ms(1000);
fprintf(FP,"hello, ready to start now!!\r\n");
output_low(SPI_MEM_CS1); // Drive CS low
spi_write(WREN_CMD); // Write enable command
spi_write(ALL_ERASE_CMD); // bulk erase command
spi_write(RDSR_CMD); // SPI read status command
data=spi_read(0); // Read first byte
i = 0;
while((data & 0x1)==1)
{
i++;
delay_ms(1000); // Wait for WIP = 0 meaning
data=spi_read(0); // Read first byte
fprintf(FP,"waiting %u seconds\r\n", i);
}
output_high(SPI_MEM_CS1); // Drive CS high
delay_ms(500); // 40s max wait
fprintf(FP,"spi data is %u. Done\r\n", data);
while(1);
}
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Ttelmah
Joined: 11 Mar 2010
Posts: 19518
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| Posted: Sat Jan 15, 2011 3:11 am |
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Bulk erase, won't start, till you raise the CS.
The sequence needs to be:
Drop chip select
Send erase command.
Raise chip select
Drop chip select
Send 'read status'
Read bytes till command finishes
Raise chip select
It is ignoring your command, because CS has not gone high after the bulk erase command.
Section 6.1 of the data sheet:
"Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated."
Best Wishes |
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FvM
Joined: 27 Aug 2008
Posts: 2337
Location: Germany
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| Posted: Sat Jan 15, 2011 3:42 am |
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| PCD V4.117 hasn't been released by CCS. Ask there. |
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miro
Joined: 15 Jan 2011
Posts: 62
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| Re: SPI is not working with PCD v4.117 |
| Posted: Sat Jan 15, 2011 9:46 am |
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Howard,
The potential issue is the spi_write() does not wait until all bits are clocked out from the chip. When you toggle the /CS after a spi_write() high, you stop the spi transmition at the memory side too early. Try this (I've found that on the C30 forum) and it works fine in C30 and pic24 (8bit mode, SPI inter. disabled):
| Code: |
// for CCS
#BIT SPI1IF =0x084.10
#BYTE SPI1BUF =0x248
#BIT SPITBF =0x240.1
#BIT SPIROV =0x240.6
#BIT SPIRBF =0x240.0
void _spi_write(unsigned char data_out)
{
SPI1IF = 0; //clear SPI IF
SPI1BUF = data_out & 0x00ff;
while(SPITBF);
while(SPI1IF == 0); // wait on on SPI Interr. Flag
data_out = SPI1BUF;
}
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Miro |
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FvM
Joined: 27 Aug 2008
Posts: 2337
Location: Germany
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| Posted: Sat Jan 15, 2011 12:13 pm |
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| Quote: | | The potential issue is the spi_write() does not wait until all bits are clocked out from the chip. |
This has been the case with previous PCD versions, where it was recommended to use spi_read() instead of spi_write(). CCS has finally changed the code, now spi_write() is identical to spi_read(), waiting for RBF before returning from the command.
The only problem I can see is, that M25P128 is not operated according to the datasheet, that requires to release nCS after every command, as Ttelmah already mentioned. I must confess, that I never tried, if it possibly works keeping nCS asserted. |
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kongfu1
Joined: 26 Apr 2010
Posts: 56
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| Re: SPI is not working with PCD v4.117 |
| Posted: Sat Jan 15, 2011 3:10 pm |
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| miro wrote: | Howard,
The potential issue is the spi_write() does not wait until all bits are clocked out from the chip. When you toggle the /CS after a spi_write() high, you stop the spi transmition at the memory side too early. Try this (I've found that on the C30 forum) and it works fine in C30 and pic24 (8bit mode, SPI inter. disabled):
| Code: |
// for CCS
#BIT SPI1IF =0x084.10
#BYTE SPI1BUF =0x248
#BIT SPITBF =0x240.1
#BIT SPIROV =0x240.6
#BIT SPIRBF =0x240.0
void _spi_write(unsigned char data_out)
{
SPI1IF = 0; //clear SPI IF
SPI1BUF = data_out & 0x00ff;
while(SPITBF);
while(SPI1IF == 0); // wait on on SPI Interr. Flag
data_out = SPI1BUF;
}
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Miro |
Miro,
Thanks a lot.
Howard |
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kongfu1
Joined: 26 Apr 2010
Posts: 56
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| Posted: Sat Jan 15, 2011 3:12 pm |
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| Ttelmah wrote: | Bulk erase, won't start, till you raise the CS.
The sequence needs to be:
Drop chip select
Send erase command.
Raise chip select
Drop chip select
Send 'read status'
Read bytes till command finishes
Raise chip select
It is ignoring your command, because CS has not gone high after the bulk erase command.
Section 6.1 of the data sheet:
"Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated."
Best Wishes |
Good points. Those were missed when I try to put all codes together for the post. Thanks.
Howard |
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kongfu1
Joined: 26 Apr 2010
Posts: 56
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| Posted: Sat Jan 15, 2011 3:22 pm |
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| FvM wrote: | | PCD V4.117 hasn't been released by CCS. Ask there. |
Correct. 4.117 is not officially released yet. I only have two things, PCD.dll 4.117 fixed RTOS and a device head file to fix spi register error. There is a memory management bug for 24FJ256GB206 (maybe other PICs) that disabled malloc/calloc as well as structure array declaration that shall be fixed in final release of 4.117 soon. |
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FvM
Joined: 27 Aug 2008
Posts: 2337
Location: Germany
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| Posted: Sat Jan 15, 2011 4:12 pm |
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| Quote: | | Those were missed when I try to put all codes together for the post. |
Do you mean, your code operates nCS correctly but still doesn't work? Then post a real application rather than some fake code!
| Quote: | | Correct. 4.117 is not officially released yet. I only have two things, PCD.dll 4.117 fixed RTOS and a device head file to fix spi register error. |
In other words, noone would be able to reproduce your results, because your PCD version uses different SPI registers? And there's a finite chance that it's just a newly introduced 4.117 bug. |
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FvM
Joined: 27 Aug 2008
Posts: 2337
Location: Germany
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| Posted: Sat Jan 15, 2011 4:20 pm |
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Perhaps it's just another case of fake code, but if this line has been correctly copied from the real application, you don't need to search why the code fails:
#pin_select SS1OUT=SPI_DATA_IN |
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