Weird SPI powerup bug

[evsource]

I've got a 18F4685 master and 18F2620 slave. Compiler PCH 4.109. I'm using the slave select line. Using mode 3. Both are running at 40mHz with external crystals.

I can get both to communicate fine if I power up the chips at the same time. If I reprogram the master while the slave is running, when the master starts running again, it does "something" weird.

Here's the "normal" data packet received from the slave when powered up together, or if I power up the slave second:

0xFC (init byte)
0x00 (data)
0x00 (data)
0x00 (data)
0xAB (end of transmission byte)

Here's the "weird" stuff I get if I power up the master second, while the slave is still running:

0xFC
0x02
0x00
0x02
0x7C
0xAB

I have no idea where the 0x02's and 0x7C are coming from. The slave is not loading that data into the SSPBUF.

I've polled the receive overflow indicator bit (SSPOV), as well as the write collision detect bit (WCOL) in SSPCON1, both of which never get set.

The master is sending data (irrelevant what it's sending, I think), at very slow intervals. A single byte is transmitted every 1ms. Hence, the data is being received at that rate.

I know a simple test program will be asked for. Thing is, it works - just not all the time. If a test program is needed to give advice, let me know and I'll strip it down to the bare bones.

Any brilliant ideas?

[evsource]

Looks like I found something to make it work, but it seems strange that I'd have to do it.

In the slave, I look for regular communications from the master - every 50ms. What I did if I don't see comm from the master in that time frame is this:

[PCM programmer]

Try putting a 10K pull-up on the \CS line. If there are two boards, the
pull-up should be on the slave board. This will hold the slave de-selected
if the Master is not present.