Should interrupts be disabled during master i2c activity?

JamesW, Kent, England · Guest

Hi folks,

A few years ago it was recommended on this forum that interrupts should be disabled when reading/writing for an I2C peripheral - so that the irq's couldn't pulse stretch the signals. (I am the bus master)

If you are using an hardware I2C SSP built into the processor - does this apply?

The reason is that I am trying to write an I2C recovery routine, that deals with what happens if a peripheral stops responding and locks the bus up. If I can use a timer interrupt, I can restart the processor after a certain time - if not - can anyone suggest an alternative method (as sometimes I2C write hangs)?

Thanks

James
James

bkamen · Posted: Mon Jan 18, 2010 12:51 pm

No, not really.

And I2C is a clocked data stream anyway, so timing is pretty flexible.

it's RS232 (software UARTs) where timing can really muck up the works.

Now, some I2C chips *might* have timeouts. So that becomes a "try it and if it breaks look deeper".

But a hardware I2C makes interrupts even more irrelevant.

-Ben
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