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Pic 18f4550

 
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Fenix
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Pic 18f4550
PostPosted: Thu Nov 12, 2009 12:59 pm     Reply with quote
I used the following settings for my design:
Code:

#FUSES HSPLL
#FUSES PLL4
#FUSES CPUDIV2
...
...
#use delay(clock=48000000)
...
void main()
{
...

setup_oscillator(OSC_16MHZ|OSC_NORMAL|OSC_PLL_ON);
...

Are they correct??
Otherwise how do I have to set a CPU at 48MHz and internal oscillator on pic 18f4550??
PCM programmer



Joined: 06 Sep 2003
Posts: 21708

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PostPosted: Thu Nov 12, 2009 1:26 pm     Reply with quote
Download the data sheets for the 18F4550 and the 18F45J50.

18F4550:
http://ww1.microchip.com/downloads/en/DeviceDoc/39632e.pdf

18F45J50:
http://ww1.microchip.com/downloads/en/DeviceDoc/39931c.pdf

Compare the oscillator diagrams in each data sheet:
Quote:
FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM

FIGURE 2-1: PIC18F46J50 FAMILY CLOCK DIAGRAM

Which one of them has a path from the Internal Oscillator Block up to
the PLL ?

Also, look in the 18F4550.h and 18F45J50.h files. Which one has a fuse
setting that would allow the Internal Oscillator to be used with the PLL ?
Quote:

#device PIC18F4550
//////// Fuses: XT, XTPLL, EC_IO, EC, ECPIO, ECPLL, INTRC_IO, INTRC,

Quote:

#device PIC18F45J50
//////// Fuses:
HS, HSPLL, EC, ECPLL, INTRC, INTRC_PLL, INTRC_PLL_IO, INTRC_IO
Fenix
Guest
PostPosted: Fri Nov 13, 2009 8:06 am     Reply with quote
I think the HS has a path from the Internal Oscillator Block up to
the PLL, but I don't know which configuration to use:
First one:
Code:

#FUSES HSPLL
#FUSES PLL4
#FUSES CPUDIV2
...
...
#use delay(clock=48000000)
...
void main()
{
...

setup_oscillator(OSC_16MHZ|OSC_NORMAL|OSC_PLL_ON);
...


or second one:
Code:

#FUSES HS
#FUSES PLL4
#FUSES CPUDIV2
...
...
#use delay(clock=48000000)
...
void main()
{
...

setup_oscillator(OSC_16MHZ|OSC_NORMAL|OSC_PLL_ON);
...
Ttelmah
Guest
PostPosted: Fri Nov 13, 2009 11:08 am     Reply with quote
I answered this only a few days ago.

First _get rid of the setup oscillator line_.

The 4550, _does not have a PLL available for the internal oscillator block. CCS _incorrectly_ include a setting for this, but the chip doesn't have it.

Use:
Code:

#FUSES HSPLL
#FUSES PLL4
#FUSES CPUDIV1
...
...
#use delay(clock=48000000)


Note the change to the CPUDIV fuse.
The 'point' here is that the fuse names CCS use, correspond to the division when the direct feed from the external clock is used, _not_ the USB PLL.

The fuses are:

CCS name Division when used with the USB clock
CPUDIV1 /2
CPUDIV2 /3
CPUDIV3 /4
CPUDIV4 /6

So to get 48MHz from the 96MHz USB clock, requires CPUDIV1. The setting you show, gives 32MHz, not 48Mhz.

Best Wishes
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