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int_ext and time required to detect falling/rising edge

 
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evsource



Joined: 21 Nov 2006
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int_ext and time required to detect falling/rising edge
PostPosted: Thu Nov 05, 2009 11:45 pm     Reply with quote

Assuming a 10mHz 16F88. Since I know PCM Programmer will ask (Very Happy), I'm using PCM 4.032.

When using #int_ext, what would the constraints be to detect an incoming pulse (either rising or falling edge, whatever the interrupt was set up for). For example, detecting a falling edge. Would it matter how long the pulse stayed low? If there was a falling edge, but 1us later, the signal went high again, would it still fire the interrupt?

I know I could test it empirically, but for future reference of others (and to save me time testing it out), I thought it would be worth asking here. I did search the forum for the answer already.
PCM programmer



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PostPosted: Fri Nov 06, 2009 2:43 am     Reply with quote

It's normally given at the end of this table, in the Electrical Specifications
section of the data sheet:
Quote:
CLKOUT AND I/O TIMING PARAMETERS

For the 16F88, the minimum External Interrupt pulse width is 1 instruction
cycle (1 Tcy):
Quote:
INT Pin High or Low Time: Tcy (Min)

With a 4 MHz oscillator, 1 Tcy is 1 usec. At 20 MHz, it's 200 ns.

Several other data sheets for similar PICs specify it as 25 ns (min).
See the 16F690 and 16F887.
FvM



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PostPosted: Fri Nov 06, 2009 4:16 am     Reply with quote

Some interrupts sources can operate also in sleep mode. In this case, the respective part of the interrupt logic can't use a system clock source and works asynchronously, reacting faster than an instruction cycle.

Last edited by FvM on Fri Nov 06, 2009 4:17 am; edited 1 time in total
Ttelmah
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PostPosted: Fri Nov 06, 2009 4:16 am     Reply with quote

You'll find the 'short' time (25nSec typically, - but not tested), is present on all chips that support 'clock switching'. Makes sense if you think about it, since otherwise the interrupt detection time would change when you switched clocks.

Best Wishes
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