16F873 - SPI Clock Speed

[john cutler]

Hi. I'm using CCS PCWH vers 3.139 but I happen to be using MPLAB6.0 right now. It's working fine. My question concerns the PIC 16F873 and the MSSP. According to the Microchip data book there are 4 possible clock modes for the hardware SSP port.

"
Fosc/4 (or Tcy)
Fosc/16 (rr4 * Tcy)
Fosc/64 (or 16*Tcy)
Timer2 output/2

This allows a maximum clock frequesncy (at 20 Mhz) of 5.0 Mhx.

"

Well I'm using a 20 Mhx clock and I have the spi_mode set for
spi_clk_div-4 and the spi is working fine, but the spi clock pin on the PIC is only spitting out 8 bit bursts @1.25 Mhz.

I measured (on a Tek 3034B scope) the system clock - it is indeed 20 Mhz. The bit clock period is 800 ns.

Anyone know why this might be so?

Thanks

John
___________________________
This message was ported from CCS's old forum
Original Post ID: 11144

[Neutone]

:=Hi. I'm using CCS PCWH vers 3.139 but I happen to be using MPLAB6.0 right now. It's working fine. My question concerns the PIC 16F873 and the MSSP. According to the Microchip data book there are 4 possible clock modes for the hardware SSP port.
:=
:="
:=Fosc/4 (or Tcy)
:=Fosc/16 (rr4 * Tcy)
:=Fosc/64 (or 16*Tcy)
:=Timer2 output/2
:=
:=This allows a maximum clock frequesncy (at 20 Mhz) of 5.0 Mhx.
:=
:="
:=
:=Well I'm using a 20 Mhx clock and I have the spi_mode set for
:=spi_clk_div-4 and the spi is working fine, but the spi clock pin on the PIC is only spitting out 8 bit bursts @1.25 Mhz.
:=
:=I measured (on a Tek 3034B scope) the system clock - it is indeed 20 Mhz. The bit clock period is 800 ns.
:=
:=Anyone know why this might be so?
:=
:=Thanks
:=
:=John

The built in functions take some time to make sure the last byte transmition has completed and load the next byte to send. That is why the clock burst one byte at a time. For the fastest possiable transmition rate you should do it all in software.
___________________________
This message was ported from CCS's old forum
Original Post ID: 11159

[john cutler]

:=:=Hi. I'm using CCS PCWH vers 3.139 but I happen to be using MPLAB6.0 right now. It's working fine. My question concerns the PIC 16F873 and the MSSP. According to the Microchip data book there are 4 possible clock modes for the hardware SSP port.
:=:=
:=:="
:=:=Fosc/4 (or Tcy)
:=:=Fosc/16 (rr4 * Tcy)
:=:=Fosc/64 (or 16*Tcy)
:=:=Timer2 output/2
:=:=
:=:=This allows a maximum clock frequesncy (at 20 Mhz) of 5.0 Mhx.
:=:=
:=:="
:=:=
:=:=Well I'm using a 20 Mhx clock and I have the spi_mode set for
:=:=spi_clk_div-4 and the spi is working fine, but the spi clock pin on the PIC is only spitting out 8 bit bursts @1.25 Mhz.
:=:=
:=:=I measured (on a Tek 3034B scope) the system clock - it is indeed 20 Mhz. The bit clock period is 800 ns.
:=:=
:=:=Anyone know why this might be so?
:=:=
:=:=Thanks
:=:=
:=:=John
:=
:=The built in functions take some time to make sure the last byte transmition has completed and load the next byte to send. That is why the clock burst one byte at a time. For the fastest possiable transmition rate you should do it all in software.

Yes, that would affect the time between bytes. It shouldn't effect the sck clock rate. That is hardware controlled once you set the clock divide_by_rate - similar to setting an on-chip timer. I realize that the CCS SPI soutines loop until each byte has been sent, but once the byte is sent to the hardware buffer be transmitted, the rate at which it is clocked is dtermined by hardware.
___________________________
This message was ported from CCS's old forum
Original Post ID: 11161

[john cutler]

Well guess what? Yet Another CCS Bug! I looked at the listing in MPLab and low and behold even though spi_clk_div_4 is being properly called, the SSPCON register has it's LSB as a 1 not a zero as it should. I put in a little

#asm
movlw #0xFE
andf 0x0014, 1

#endasm

Now, since the lsb is a 0, the SPI clock rate is correct and I get the 5 Mhz I wanted.

I'll write CCS now.

Thanks.

John





:=:=:=Hi. I'm using CCS PCWH vers 3.139 but I happen to be using MPLAB6.0 right now. It's working fine. My question concerns the PIC 16F873 and the MSSP. According to the Microchip data book there are 4 possible clock modes for the hardware SSP port.
:=:=:=
:=:=:="
:=:=:=Fosc/4 (or Tcy)
:=:=:=Fosc/16 (rr4 * Tcy)
:=:=:=Fosc/64 (or 16*Tcy)
:=:=:=Timer2 output/2
:=:=:=
:=:=:=This allows a maximum clock frequesncy (at 20 Mhz) of 5.0 Mhx.
:=:=:=
:=:=:="
:=:=:=
:=:=:=Well I'm using a 20 Mhx clock and I have the spi_mode set for
:=:=:=spi_clk_div-4 and the spi is working fine, but the spi clock pin on the PIC is only spitting out 8 bit bursts @1.25 Mhz.
:=:=:=
:=:=:=I measured (on a Tek 3034B scope) the system clock - it is indeed 20 Mhz. The bit clock period is 800 ns.
:=:=:=
:=:=:=Anyone know why this might be so?
:=:=:=
:=:=:=Thanks
:=:=:=
:=:=:=John
:=:=
:=:=The built in functions take some time to make sure the last byte transmition has completed and load the next byte to send. That is why the clock burst one byte at a time. For the fastest possiable transmition rate you should do it all in software.
:=
:=Yes, that would affect the time between bytes. It shouldn't effect the sck clock rate. That is hardware controlled once you set the clock divide_by_rate - similar to setting an on-chip timer. I realize that the CCS SPI soutines loop until each byte has been sent, but once the byte is sent to the hardware buffer be transmitted, the rate at which it is clocked is dtermined by hardware.
___________________________
This message was ported from CCS's old forum
Original Post ID: 11164

[john cutler]

I stand corrected!! I had improperly put "spi_ss_disabled" or'ed with the spi_master | spi_xmit_l_to_h | spi_clk_div_4 and this apparently made the CCS setup_spi routine use a wrong value for spi_clk_div_4.

I must say CCS responded very quickly and pointed out my error.

Another lesson in rush_to_judgement/humility for me
___________________________
This message was ported from CCS's old forum
Original Post ID: 11175