Low Power frequency(pulse) scaler algorithm

[adfkk]

Hi.
I am trying to design Low power(meaning running as little as possible)
frequency(pulse) scaler.

First, i designed the prototype using algorithm that uses counter over flow interrupt.
For example, if divider is 4, there should be interrupt every four pulse inputs. Thus, I would set counter to Max-n+1 so that it interrupts on overflow.
The real problem is when the divider is not an integer.

For example, if the divider is 5.34, I can no longer use above algorithm.

I tried calculating input frequency directly and converting that to output frequency. However, it was very hard to generate accurate ratio of output freqeucy.

Any solutions to this design problem? Hardware or Software.

I will appreciate any responses. Thanks

[Guest]

This is called a "fractional n divider" and is used extensively in frequency synthesis and direct digital synthesizer design.

Google: fractional n divider and you will see the various methods that can be used.

If you are running very slow on the inputs you might be able to pull something off in the PIC, but you will more probably need a PLD or frequency synthesizer solution with external chips.

HTH - Steve H.