Nested interrupts / Interrupt priority on PIC16Fxxx

[ckrusen]

I want to respond to an IOC on a PORTA pin while in the RTCC interrupt.

Can interrupts be re-enabled inside an ISR?

If so, do I need to do anything special before exiting either the original ISR or the one that interrupted the original ISR?


Micro: PIC16F688
Compiler: PCM 3.235


Thanks
_________________
Calvin

[Ttelmah]

At heart, you can't....
The PIC _hardware_ disables the global interrupt flag, when the interrupt handler is called.
There is only one main interrupt vector, which is called when any interrupt event occurs. If the global interrupt was re-enabled, the _same_ vector would get called.
The PIC does not support re-entrancy (calling code inside itself), which this would imply...
Basically, you can only do this, by chosing a later PIC, that supports more than one interrupt hardware vector (PIC18)

Remember though, that there is nothing to stop you _polling_ the second interrupt flag inside the RTCC code. This will almost certainly be faster anyway...

Best Wishes

[ckrusen]

Then why does the C compiler require designation of the ISR?
For example,

[Ttelmah]

CCS, doesn't really....

You can just use #INT_GLOBAL, and this replaces the 'master' interrupt handler.

What CCS does, is generate a 'hidden' master handler for you, that saves all the registers (All registers used inside the interrupt service routines need to be saved), then tests each interrupt bit, and calls the associated subroutine.

Even chips like the 80x86, only have a couple of 'real' interrupt levels, but what they then have is an external interrupt 'controller', which allows multiple inputs, with different priorities, and the chip hardware, then allows different vectors to actually be created by these chips, and vector you to different routines. These processors also have hardware stacks for user variables, so that code can be re-entrant.

Best Wishes