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LST file registers for USART

 
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abq_guy



Joined: 26 Jan 2009
Posts: 13

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LST file registers for USART
PostPosted: Wed Apr 15, 2009 10:13 am     Reply with quote

Hello,

#use rs232 (baud=850000, xmit=PIN_C6, rcv=PIN_C7, parity=N, bits=8, BRGH1OK, STREAM=COM_A) //compiles OK

I am setting the baud rate to 850000 bps, and the compiler generates the following LST file.

015E: BTFSS F9E.4
0160: BRA 015E
0162: MOVWF FAD
0164: RETLW 00

How do I infer what is in the BRG16 and BRGH and the SYNC bit is being set to from the LST file ? The LST file is refereing to location FAD, which is the TXREG1 register.

I am lost, Please help. Also If I want to set these registers myself, how can I do it ?


Thanks,

abq_guy
PCM programmer



Joined: 06 Sep 2003
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PostPosted: Wed Apr 15, 2009 10:23 am     Reply with quote

Set the list file format to "Symbolic" mode. Look in the Project / Build
Options menu for this setting. Then the names of the registers will
appear in the .LST file instead of their addresses.
ckielstra



Joined: 18 Mar 2004
Posts: 3680
Location: The Netherlands

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PostPosted: Wed Apr 15, 2009 10:25 am     Reply with quote

The part of the list file you show here is for transmitting the data, not for configuring the UART. The code for configuring the UART is most likely at the start of main().

Quote:
If I want to set these registers myself, how can I do it ?
set_uart_speed()
abq_guy



Joined: 26 Jan 2009
Posts: 13

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PostPosted: Wed Apr 15, 2009 10:43 am     Reply with quote

Thanks PCM_programmer. That worked. I can see the register names now.

Thanks Ckielstra. Is there a baud rate limit on the set_uart_speed(). The manual mentions it is 115kbps.

Thanks,

abq_guy
Ttelmah
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PostPosted: Wed Apr 15, 2009 3:04 pm     Reply with quote

You can go well over 115K, _but_ you run into the limitations on the available divisors, and clock rates. The 115K limit, was applicable to older compilers, but I have run 'unusual' rates, like 500K, with a chip at 40Mhz, fine. 850000, is probably going to actually be giving perhaps 833333Hz. Basing this on a likely master clock of 40Mhz, then the clock feeding the BRG, will be 10Mhz, and this /12, gives the closest match to 850K. This is 2% in error, which the compiler will accept (it'll warn if the rate is badly wrong). You would actually be 'better' at something like 34MHz master clock for this rate. However, with a byte time of just under 12uSec, you are going to have to be _very_ careful with your code. No interrupt handling, and if data is arriving 'unheralded', a very tight wait loop will be needed.....

Best Wishes
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