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AZ APPS 1 Guest
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PSP read problem |
Posted: Fri Feb 13, 2009 6:12 pm |
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I'm using a pic18f4520.
I set up a psp interface to talk with an fpga which runs a master that machine that I wrote.
Every time I tell the FPGA to write to the pic, I get the correct data in the pic. I can see it on a monitor via the pic's rs232 interface.
If I do a single write to the pic followed by a read, then it works. My FPGA LEDs show me the correct data that I read from the PIC.
However, when I do a series of write then reads, I always get the same problem.
Let's say the FPGA writes ABCD and expects to get back EFGH. On my screen I always see ABCD. However, the FPGA leds show me H, then E, then F, then G (i put a 1 sec delay in between each write-read loop) This off-by-one problem seems to indicate that the PIC read buffer isn't being cleared from the last time I ran the FPGA.
There are 3 specific issues I'm wondering about:
1- Do I need to control the PIC tri-state buffers for the data lines specifically? I looked up the psp in the ccs manual and in the pic examples directory, and neither piece of code actually uses set_tris_d. It seems like the setup_psp() function is supposed to do that.
2- I read the pic manual, and it shows you how to construct the correct wr/rd waveforms to control the pic. However, it doesn't seem to say how long to leave the hardware alone after reading before writing again. In my state-machine, I err on the side of caution and give it several milliseconds. However, I am wondering if the pic is still recovering from a read when I write to it again. After writing to the pic, I then wait for the pic to assert an ack line (which tells me its done receiving and processing the write) before reading from it. But there is no handshaking following the read.
3- Finally, I am wondering whether the psp read code correctly clears the obuf. Maybe I should find an assembly language function to explicitly control the registers?
Here is my psp_isr() and main():
Code: | int psp_err=0;
char data=0;
char junk=0;
char response='`';
#INT_PSP
void psp_isr () {
porta.ack=0;
if(porta.pic_mode) {
delay_ms(1000);
while(!psp_input_full());
if (psp_overflow()) {
psp_err=true;
putc_a('x');
junk=PSP_DATA;
}
else {
data=PSP_DATA;
putc_a(data);
switch(data) {
case 'a':
response='e';
break;
case 'b':
response='f';
break;
case 'c':
response='g';
break;
case 'd':
response='h';
break;
default:
my_transmit_a("Default case!!!!",1);
break;
}
}
porta.ack=1;
}
else{
data=response;
while(psp_output_full());
psp_data=data;
}
}
void main(void) {
setup_oscillator(OSC_32MHZ);
delay_ms(1000);
disable_interrupts(global);
set_tris_a(0xF7);
set_tris_b(0xF0);
setup_psp (PSP_ENABLED);
delay_ms(500);
enable_interrupts(INT_PSP);
enable_interrupts(global);
while(1) { }
} |
Note- I scoped the pic_mode and ack signals to make sure they were properly connected to pins and asserted at the correct times.
This really seems like I'm having a problem with the pic psp read buffer. So far the FPGA has done exactly what I told it to at every step, so I'm not too concerned about the pmp master state machine.
I would sincerely appreciate any help anyone could offer me. I found this problem this morning and spent the entire day trying to solve it. If I can't find a solution I'll have to get a logic analyzer and spend hours checking signals manually.
Thanks very much in advance. |
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PCM programmer
Joined: 06 Sep 2003 Posts: 21708
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Posted: Sun Feb 15, 2009 12:43 am |
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Post your #include, #fuses, and #use delay() statements, just so we can
make sure there are no problems there before we look further.
Also post your compiler version. |
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AZ APPS 1 Guest
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psp read problem |
Posted: Sun Feb 22, 2009 1:31 pm |
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Sorry about the delay in responding. We've been busy with other projects lately, so I've had very little time to get back to the psp.
My compiler is PCH 4.016.
Code: | #include <18F4520.h>
#device PASS_STRINGS = IN_RAM
#device HIGH_INTS=TRUE
#include <stdio.h>
#include <string.h>
#use delay(INTERNAL=8M, clock=32M)
#fuses INTRC//, DEBUG
#priority psp |
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