why my #INT_SSP active only one time(power up)

[norman_tan]

Hi, all
I am using a PIC16F883 chip(as slave) to communicate with a master(Freescale MCU) via I2C bus(clk = 5khz), but I found interrupt only happens one time after power on. I have settings below:

[PCM programmer]

[norman_tan]

But, sorry Sir. The master sends address "0x01", it is not decided by slave.
As a slave, in this project, it is only a dummy. that is to say, it only receives data from master and displays it.
Another question is: the first bye from master is "0x01" but it is a write command(according to format of I2C, "0x01" = Address(0x00) + R/W(1), there should be a READ command) I am sure what I fetched with scope is right and it also matched what customer said.
I tried as what you said but there is still not action for it.

[Ttelmah]

I2C, has it's address organised, as the _upper seven bits_ in the address 'byte'.

The low bit, is _reserved_ for the direction control bit. Note the the keyword 'reserved' here.

Hence _I2C, does not allow odd addresses_. Address '0', used in a device, implies that '0b00000000' will be used for write accesses, and '0b00000001, will be used for read accesses. You cannot have 'address 1', since it is _already used by the device at address 0_.

Then I2C, has a number of 'reserved' addresses. '0', is the 'general call address'. This is reserved, for a master device to be able to access _all_ devices on the bus. Using the address byte '1', is a general call address read operation, and is defined in I2C, as the 'START' byte. It is not useable as a normal address.

Now, the first thing to check, is whether your 'master', specifies it's addresses in 8bit, or 7bit format. Some manufacturers (Texas for example), give the addresses as just the upper seven bits, without the direction control bit. For these, 'address 1', would be accessed using the PIC, as address _2_. Now, this is still a 'reserved' address (actually the CBUS address byte), and the I2C specification specifically says "The CBUS address has been reserved to enable the intermixing of CBUS compatible, and I2C bus devices on the same system. I2C compatible devices _are not allowed_ to respond to the reception of this address"...

So, _if your master device is sending as an address '1'_, it is acting illegally. If there is only one slave device on the bus, and this is required to be a 'write' operation, then you may be able to get it to work, by enabling general call address support, or selecting address _0_ on the slave device. However if this is not what it is doing, you need to get the master device modified, to comply with the I2C spec. If you can't get that done, you may as well give up'....

Best Wishes

[norman_tan]

Thanks! Sir.
You are right! It is just what you said, Customer told me yesterday the Address was 8-bit format.
There are more than one slave on bus, Address "0x01" only stands for the slave_1 address, and "0x02" for the second slave_2, and so on..
Customer also said there were no ACKs from slave, but from signals fetched by scope, there are acks at every 9th SCL clock(signals are made up: "<START><ADDRESS><COMMAND><DATA><STOP>"), I don't know who generates the ACKs.
Will 8-bit Address possibly cause no respondence for I2C interrupt for PIC chip? I really don't know how to deal with these signals with I2C ports on PIC chip now!
I am sorry I don't know how to enclose a picture here. [/url]

[norman_tan]

Since it is an irregular I2C format, So I could not use the standard I2C hardware to match it(it won't lead a correct result forever).
Chip(Freescale MCU) used by vendor has not an I2C peripheral, So they must generate signals by simulating I2C format. since that, I can also simulate an I2C receiver.
The other day, I did that and got a perfect result. I only took SDA and SCL as general I/O pins.

Thanks so much for your help!