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Can PIC16F87 run I2C at 100kHz as a slave?

 
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xenogear3



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Can PIC16F87 run I2C at 100kHz as a slave?
PostPosted: Sat Jun 14, 2008 6:36 am     Reply with quote

I have a PIC16F87. It uses the internal 8MHz clock and runs as an I2C slave.

It works fine if the master I2C device runs at 60kHz.

However, if the master I2C device runs at 100kHz and sends a read request, the PIC16F87 never acknowledged.

Any ideas?
Will a faster CPU clock help?
Ttelmah
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PostPosted: Sat Jun 14, 2008 6:56 am     Reply with quote

It should handle 100K fine. However how long it'll take to respond, does depend on the clock, so there can be problems if you have a 'master' at (say) 20MHz, and then the slave at (say) 4mHz. Unless your clock is low though, I'd be double checking that you have got adequate pull-ups. Though between 60K, and 100K, is 'low' for problems here, the value needed does fall with increasing signal frequency, and if the bus capacitance is high, problems could appear down here. Also the need to series resistors in the lines to help prevent ringing, also increases with frequency.

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drh



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PostPosted: Sat Jun 14, 2008 10:23 am     Reply with quote

The other things to concider are the value of the pullup resistors and the length of the connection between the master and slave devices. There are limits to the bus capacitance and minimum and maximum pullup resistance.
What value are your pullup resistors?
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David
xenogear3



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PostPosted: Sun Jun 15, 2008 7:29 am     Reply with quote

The pullup resistor is 4.7k ohms. The Vcc (bus voltage) is 5 volts.
It goes through a short (2 inches) ribbon cable.
There is no bus capacitance and serial resistor.

I can control the I2C master device's SCL clock rate. If I set it at 60kHz, everything works fine.

If I set it at 100kHz, the slave device (PIC16F87) acknowledged when the master tried to write.

The problem is the read. The slave never acknowledged.
drh



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PostPosted: Sun Jun 15, 2008 10:02 am     Reply with quote

Doesn't sound like a "bus" problem, although I would try 2.7K pullups.
What is the slave doing to respond to a read from the master? Is it holding the SCL line while trying to respond? Does the master handle this properly?
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David
xenogear3



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PostPosted: Sun Jun 15, 2008 12:02 pm     Reply with quote

What is the slave doing to respond to a read from the master?

At 100kHz, nothing. It acts like "never see the address". No SCL hold and no interrupt.

This PIC (16F87) uses "SSP".
Do you think the PIC with MSSP (such as PIC16F883) will help?
Ttelmah
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PostPosted: Sun Jun 15, 2008 2:58 pm     Reply with quote

A comment. _Of course there is bus capacitance_. As soon as you have any electrical conductor, near another, you have capacitance between them.
Bus capacitance, is not something you voluntarily add, it is a property of the bus, which degrades it's high frequency performance. it is made worse, by capacitance from the chip pins themselves, and from your resistors. For a 5v powered bus, with no series resistors, the minimum value for the pull up resistors, is 2KR. With a 4K7 pull up, the bus capacitance, must be below 180pF, for reliable operation at 100KHz. With 2K2 resistors, the allowable capacitance rises to 400pF.

Best Wishes
drh



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PostPosted: Mon Jun 16, 2008 8:28 am     Reply with quote

Quote:
What is the slave doing to respond to a read from the master?

At 100kHz, nothing. It acts like "never see the address". No SCL hold and no interrupt.

What I meant to say was what is the slave code doing to respond to a "read" from the master.
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David
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