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Clearing CCP timer

 
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Langton



Joined: 29 Nov 2009
Posts: 27

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Clearing CCP timer
PostPosted: Tue Dec 30, 2025 5:38 pm     Reply with quote

Hi Guys and Gals,

Got an issue that is doing my head in.
Using XIDE 6.00 with PCD1.22 on a dsPIC33CK256MP202

I need accurate timing for a digital input that I am utilising the high speed comparator for. When I refresh it e.g. try to zero the CCP2 timer, it only clears CCP2TMRH. I have tried to thrash it out with AI, but am not getting much traction there. I've tried manually clearing the registers + switching the CCP off and clearing it etc, but it does not allow me to switch it off when running. Reading is no issue at all.

setup is...
SETUP_CCP2( CCP_TIMER | CCP_DIV_BY_64 | CCP_SYSTEM_CLOCK | CCP_TIMER_32_BIT);

and to clear...
SET_TIMER_CCP2(0);

Any advice would be much apprechiated
happy new year Smile
Ttelmah



Joined: 11 Mar 2010
Posts: 20012

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PostPosted: Tue Dec 30, 2025 11:49 pm     Reply with quote

Don't.
For accuracy, simply leave the timer running. Then store the value, and
subtract this from the next value.
Problem with writing the registers, is that you have to do two separate
writes first to the low 16bit register, and then to the high registers. Since
the prescaler is still running, you can get an update between the two
writes, and the count could therefore already be one, when the second
write is done. Accuracy is therefore never going to be good.
If you want to reset the timer, you just disable, and re-enable the CCP
module. This automatically resets the timer. Just define the CCPON bit
with a #bit instruction, and set it to 0, then 1. Nothing changes, except
the timer stops for the instruction when it is off, and the timer is cleared.
The great thing here is this also resets the prescaler. So everything is
genuinely zero.
CCP2CON1L bit 15
Langton



Joined: 29 Nov 2009
Posts: 27

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PostPosted: Wed Dec 31, 2025 5:46 pm     Reply with quote

Thanks Ttelmah, I just tried it and it worked perfectly and is not super stable. Thanks soooo much and have a wonderful 2026
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